Caches and Write Buffer
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
4-13
4.4.2
Enabling and disabling the write buffer
You cannot directly enable or disable the write buffer. However, setting the properties
of a memory region to be NCNB or disabling the protection unit prevents the write
buffer from being used.
0
1
NCB (Noncachable, bufferable).
Reads and writes are not cached. They always perform accesses on the AMBA ASB
interface.
Writes are placed in the write buffer and appear on the AMBA ASB interface. The
CPU continues execution as soon as the write is placed in the write buffer.
Reads can be externally aborted. Writes cannot be externally aborted.
Cache hits never occur under normal operation. If the DCache hits for this type of
access, there has been a programming error. This error is treated like a write-through
in that the DCache line is updated and the data is buffered.
Swap instruction operations on data in an NCB region are made to perform NCNB
type accesses and are not buffered.
1
0
WT (Write-through).
Reads that hit in the cache read the data from the cache and do not perform an access
on the AMBA ASB interface.
Reads that miss in the cache cause a linefill.
Writes that hit in the cache update the cache but do not mark the cache line as dirty.
All writes are placed in the write buffer and appear on the AMBA ASB interface.
The CPU continues execution as soon as the write is placed in the write buffer.
Reads and writes cannot be externally aborted.
1
1
WB (Write-back).
Reads that hit in the cache read the data from the cache and do not perform an access
on the AMBA ASB interface.
Reads that miss in the cache cause a linefill.
Writes that hit in the cache update the cache and mark the appropriate half of the
cache line as dirty. They do not cause an AMBA ASB interface access.
Writes that miss in the cache are placed in the write buffer and appear on the AMBA
ASB interface. The CPU continues execution as soon as the write is placed in the
write buffer.
Cache write-backs are buffered.
Reads, writes, and write-backs cannot be externally aborted.
Table 4-2 Data write modes (continued)
GCd
GBd
Access mode