Glossary
Glossary-4
Copyright 1999, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
ICache
A block of on-chip fast access memory locations, situated between the processor and
main memory, used for storing and retreiving copies of often used instructions. This is
done to greatly reduce the average speed of memory accesses and so to increase
processor performance.
Instruction cache
See
ICache
.
Joint Test Action Group
The name of the organization that developed standard IEEE 1149.1. This standard
defines a boundary-scan architecture used for in-circuit testing of integrated circuit
devices. It is commonly known by the initials JTAG.
JTAG
See
Joint Test Action Group
.
Little-endian
Byte ordering scheme in which bytes of increasing significance in a data word are
stored at increasing addresses in memory. See also
Big-endian
and
Endianness
.
Macrocell
A complex logic block with a defined interface and behavior. A typical VLSI system
will comprise several macrocells (such as an ARM9E-S, an ETM9, and a memory
block) plus application-specific logic.
Prefetch abort
An indication from a memory system to a core that it should halt execution of an
attempted illegal memory access. A prefetch abort can be caused by the external or
internal memory system as a result of attempting to access invalid instruction memory.
See also
Data abort
,
External abort
and
Abort
Processor
A contraction of microprocessor. A processor includes the CPU or core, plus additional
components such as memory, and interfaces. These are combined as a single macrocell,
that can be fabricated on an integrated circuit.
Region
A partition of instruction or data memory space.
Register
A temporary storage location used to hold binary data until it is ready to be used.
SBO
See
Should be one
.
SBZ
See
Should be zero
.
SCREG
The currently selected scan chain number in an ARM TAP controller.
Should be one
Should be written as 1 (or all 1s for bit fields) by software. Writing a 0 will produce
UNPREDICTABLE results.
Should be zero
Should be written as 0 (or all 0s for bit fields) by software. Writing a 1 will produce
UNPREDICTABLE results.
Tag bits
The index or key field of a CAM entry.
TAP
See
Test access port
.