ARM940T Signal Descriptions
A-6
Copyright 199, 2000 ARM Limited. All rights reserved.
ARM DDI 0144B
SDOUTBS
Input
Boundary scan serial output data. This is the serial data out of the boundary scan
chain (or other external scan chain). It must be set up to the rising edge of
TCK
.
When an external boundary scan chain is not connected, this input must be tied
LOW.
SHCLK1BS
Output
Boundary scan shift clock phase 1. This control signal is provided to ease the
connection of an external boundary scan chain.
SHCLK1BS
is used to clock the
master half of the external scan cells. When in the SHIFT-DR state of the state
machine and scan chain 3 is selected,
SHCLK1BS
follows
TCK1
. When not in
the SHIFT-DR state, or when scan chain 3 is not selected, this clock is LOW. When
an external boundary scan chain is not connected, this output must be left
unconnected.
SHCLK2BS
Output
Boundary scan shift clock phase 2. This control signal is provided to ease the
connection of an external boundary scan chain.
SHCLK2BS
is used to clock the
slave half of the external scan cells. When in the SHIFT-DR state of the state
machine and scan chain 3 is selected,
SHCLK2BS
follows
TCK2
. When not in
the SHIFT-DR state, or when scan chain 3 is not selected, this clock is LOW. When
an external boundary scan chain is not connected, this output must be left
unconnected.
TAPID[31:0]
Input
This is the ARM940T device identification (ID) code test data register, accessible
from the scan chains. It must be tied to an appropriate value when the device is
instantiated.
TAPSM[3:0]
Output
TAP controller state machine. This bus reflects the current state of the TAP
controller state machine. These bits change off the rising edge of
TCK
.
TCK
Input
Test clock. The JTAG clock (the test clock).
TCK1
Output
TCK
, phase 1.
TCK1
is HIGH when
TCK
is HIGH, although there is a slight
phase lag because of the internal clock non-overlap.
TCK2
Output
TCK
, phase 2.
TCK2
is HIGH when
TCK
is LOW, although there is a slight
phase lag because of the internal clock non-overlap.
TDI
Input
Test data input. JTAG serial input.
TDO
Output
Test data output. JTAG serial output.
Table A-3 JTAG and TAP controller signals (continued)
Name
Direction
Description