Caches and Write Buffer
ARM DDI 0144B
Copyright 1999, 2000 ARM Limited. All rights reserved.
4-9
4.3.2
Operation of the GCd bit and GBd bit
The GCd bit determines if data being read must be placed in the DCache and used for
subsequent reads. Typically, main memory is marked as cachable to reduce memory
access time and therefore increase system performance. It is usual to mark I/O space as
noncachable. For example, if a processor is polling a memory-mapped register in I/O
space, it is important that the processor is forced to read data direct from the external
peripheral, and not from a copy of initial data held in the DCache.
The GBd and GCd bits affect writes that both hit and miss in the DCache. For details of
the ways these bits are decoded to perform different types of writes, see
The write buffer
on page 4-12.
4.3.3
DCache operation
When the DCache is enabled, it is searched when the processor performs a data load or
store. If the cache hits on a load, data is returned to the core regardless of the state of
the GCd bit. If the cache read misses, the GCd bit is examined:
If the GCd bit is 1, the cachable data area and protection unit are enabled. A
linefill of four words is performed, and the data is written into a randomly chosen
line in the DCache.
If the GCd bit is 0, a single or multiple external access is performed and the cache
is not updated.
Stores that hit in the cache always update the cache line, regardless of the GCd bit.
Stores that miss the cache use the GCd and GBd bits to determine if the write is buffered
(see
The write buffer
on page 4-12). A write miss is not loaded into the cache as a result
of that miss.
Noncachable load multiples and
NonCachable NonBufferable
(NCNB) store multiples
are broken up on 4KB boundaries (the minimum protection region size), allowing a
protection check to be performed in case the
Load Multiple
(
LDM
) or
Store Multiple
(
STM
)
crosses into a region with different protection properties.
DCache lockdown is supported with 16-word granularity. Data that is locked down
always hits on DCache searches, and lines containing locked down data cannot be
selected for replacement during a linefill.
Back-to-back stores from adjacent store instructions to the same segment within the
DCache cause a cache stall, requiring two cycles for the cache write. A burst of stores
from a single store multiple instruction does not cause stalls and allows one write per
cycle to be performed. Single back-to-back stores to different segments are also
performed without a stall, allowing one write per cycle.