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参数资料
型号： ORSO42G5-EV
厂商： Lattice Semiconductor Corporation
文件页数： 10/153页
文件大小： 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
标准包装： 1
系列： ORCA® 4 系列
类型： FPGA
适用于相关产品： ORSO42G5
所含物品： 板，线缆，电源
其它名称： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
107
30A0D
[0]
RSVD
00
Reserved
—
[1]
SYNC4_B_OVFL
SYNC8_OOS = 1 indicates that the alignment
FIFO(s) in the links in block B are near overow
(i.e., at the time of writing into address 0, the
read address was less than RX_FIFO_MIN)
SONET
[2]
SYNC2_B2_OVFL
SYNC2_B2_OVFL = 1 indicates that the align-
ment FIFO(s) in the links BC and BD are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[3]
SYNC2_B1_OVFL
SYNC2_B1_OVFL = 1 indicates that the align-
ment FIFO(s) in the links BA and BB are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[4]
SYNC4_A_OVFL
SYNC4_A_OVFL = 1 indicates that the align-
ment FIFO(s) in the links in block A are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[5]
SYNC2_A2_OVFL
SYNC2_A2_OVFL = 1 indicates that the align-
ment FIFO(s) in the links AC and AD are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[6]
SYNC2_A1_OVFL
SYNC2_A1_OVFL = 1 indicates that the align-
ment FIFO(s) in the links AA and AB are near
overow (i.e., at the time of writing into address
0, the read address was less than
RX_FIFO_MIN)
SONET
[7]
SYNC8_OVFL
SYNC8_OVFL = 1 Indicates that the alignment
FIFO(s) in eight-links are near overow (At the
time of writing into address 0, the read address
was less than RX_FIFO_MIN)
SONET
30A0E
[0:2]
RSVD
00
Reserved
—
[3]
BDL_ALIGN_ERR_B2
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs BC and BD
Cell
[4]
BDL_ALIGN_ERR_B1
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs BA and BB
Cell
[5]
BDL_ALIGN_ERR_A2
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs AC and AD
Cell
[6]
BDL_ALIGN_ERR_A1
Alignment Error, BDL_ALIGN_ERR = 1 indi-
cates that an alignment error has occurred in
the link group pairs AA and AB
Cell
[7]
BDL_ALIGN_ERR_ALL8
BDL_ALIGN_ERR_ALL8 = 1 -indicates that an
alignment error has occurred in cell group of all
eight-links
Cell
Table 36. Common Control Register Descriptions – ORSO82G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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相关代理商/技术参数
参数描述
ORSO82G5 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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