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参数资料
型号： ORSO42G5-EV
厂商： Lattice Semiconductor Corporation
文件页数： 111/153页
文件大小： 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
标准包装： 1
系列： ORCA® 4 系列
类型： FPGA
适用于相关产品： ORSO42G5
所含物品： 板，线缆，电源
其它名称： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
60
Figure 46. ORSO82G5 Receive FPGA/Embedded Core Interface IPC8 Mode
In the SERDES-only mode the data are simply transferred as 32-bit wide words to and from the FPGA logic. The
next sections describe the signal denitions for the TX and RX paths in the SONET, OPC2 and OPC8 modes. The
signal names unique to an operating mode are preferred for design and are generally the ones used in the
ispLEVER design environment. The labels in the left most column are the hardware FPGA interface names. The
ispLEVER software creates an HDL module with specic names based on the mode selected for each channel.
The pin mappings performed by ispLEVER are shown in Table 11 through Table 14.
The interface signals for the embedded RAM are completely independent of these signals. The memory signals are
described in a later section.
Signal Description for TX Path (FPGA to SERDES Core) – ORSO42G5
Signals are divided across four channels with 40 signals per channel. TXDxx[39:0] is the set of 40 signals for a
channel xx.
The data signals multiplexing scheme is similar to the one used for the RXD signals. However, the status signals
multiplexing is different. Please refer to Table 11 for a detailed description of the TXD multiplexing scheme.
For all channels the TXDxx[39:33] signals are not used.
Table 11 summarizes the signals at the FPGA/Core interface in the transmit direction.
SYSCLK156x[1,2]
IPC8_CELLSTART
D
DDD
D
DD
D
DDDD
“n” clk cycles
4 clk cycles
CELL BIP ERROR
If a Cell BIP Error occurs, the CELL_BIP_ERR signal
reects the occurrence, as shown in the figure.
D
IPC8_CELL_BIP_ERR
IPC8_CELLDROP
IPC8_[159:0]
BIP Error is associated
with CURRENT cell
Cell Drop is associated with
the NEXT cell (NOT present)
CELL BIP ERROR
If a cell error occurs within the ASB and;
1. CELL_BIP_INH=0 (Do not drop BIP errored cells)
2. A BIP error occurs
The drop indicator will PRECEED the user cell that con-
tains the BIP error. All data will be passed w/o modica-
tion.
1 cycle
IDLE
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相关代理商/技术参数
参数描述
ORSO82G5 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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