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| 型号： | ORSO42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 46/153页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL DEV PLATFORM ORSO42G5 |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORSO42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORSO42G5EV |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
14
convention is used for the ORSO42G5. Slice A contains channels AC and AD while Slice B contains channels AC
and AD.
Each SERDES block contains its own dedicated PLLs for transmit and receive clock generation. The user provides
a reference clock of the appropriate frequency (one per SERDES block). The receiver PLLs extract the clock from
the serial input data and retime the data with the recovered clock. Clock divider circuitry also provides reference
clocks for the FPGA logic.
8:32 MUX and 32:8 DEMUX
The purpose of the MUX/DEMUX block is to provide a wide, low-speed interface at the FPGA portion of the
ORSO42G5 and ORSO82G5 for each channel or data lane. The interface to the SERDES macro runs at 1/8th the
bit rate of the data lane. The MUX/DEMUX converts the data rate and bit-width so the FPGA core can run at 1/4th
this frequency (i.e., 1/32nd the SERDES rate). This gives a range of 18.75 MHz-84.38 MHz for the data crossing
the FPGA/embedded core boundary on SERDES only and SONET modes.
SONET Transmit OverHead (TOH) Processing, Framer and Scrambler/Descrambler (SONET and Cell
Modes)
In the transmit direction, the TOH block is responsible for processing the 144 (48 x 3) TOH bytes at the beginning of
each row of the transport frame. The TOH bytes may be transmitted transparently from the FPGA logic or may be
inserted by the TOH block (AUTO_SOH and AUTO_TOH modes).
The TOH block can performs A1/A2 corruption by inverting the A1/A2 bytes under software control. The block can
also force B1 errors by inverting the B1 byte or inject a fault indication by forcing the K2 byte to “00000110”. In the
receive direction, the errors will be detected and alarms set. In SONET mode, all TOH bytes can optionally be sent
transparently from the FPGA.
For each of the receive channels, the framer logic outputs four bytes (32-bits) of received data that are frame-
aligned and a frame pulse that is one clock-wide. The framer is responsible also for detecting the in-frame and Out-
Of-Frame status of the incoming data and sends out alarms (interrupts) on detecting an Out-Of-Frame (OOF) state.
In the transmit direction, the scrambler logic scrambles the outgoing data using the standard SONET polynomial 1
+ x
6 + x7. In the receive direction, the descrambler logic descrambles the incoming data using the same polynomial.
Multichannel Alignment FIFO and SPE Generation (for SONET mode)
In SONET mode, the incoming data on the channels can be independent of one another or can be synchronized in
several ways. Two channels within a SERDES block can be aligned together. Alternately, four channels can be
aligned to form a communication channel with a bandwidth of 10 Gbps. Finally, in the ORSO82G5, the alignment
can be extended across all of the SERDES to align all eight channels.
Individual channels within an alignment group can be disabled (i.e., power down) without disrupting other channels.
A disabled channel can also be aligned to its group without a disruption to the remaining channels. This holds true
only if the disabled channel had been previously enabled during alignments.
Cell Extraction, Striping and Destriping (for Cell Mode)
In the cell mode, cells are distributed across two-links or, in the ORSO82G5, across eight-links. In the TX direction,
cell data from the FPGA are “striped” across links within a link group. In the receive direction cell processing blocks
extract cells from the link groups and send them to the FPGA. This function is referred to as “destriping”.
Loopback - Overview
There are two types of loopback that can be utilized inside the embedded core of the ORSO42G5 and
ORSO82G5, near end loopback and far end (line side) loopback. Both of these loopbacks are controlled by control
registers inside the ORSO42G5 and ORSO82G5 core, which are accessible from the system bus and the Micro-
Processor Interface (MPI).
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORSO82G5 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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