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| 型号： | ORSO42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 78/153页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL DEV PLATFORM ORSO42G5 |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORSO42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORSO42G5EV |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
30
– E1 - Section order wire byte - This byte carries local orderwire information, which provides for a 64 Kbps
voice channel between two Section Termination Equipment (STE) devices.
– F1 - Section user channel byte - This byte provides a 64 Kbits/s user channel which can be used in a propri-
etary fashion.
– D1, D2, D3 - Section Data Communications Channel (SDCC) bytes - These bytes provide a 192 Kbits/s
channel for transmission of information across STEs. This information could be for control and conguration,
status monitoring, alarms, network administration data etc.
Line Overhead Bytes:
– H1, H2 - STS Payload Pointers (H1 and H2) - These bytes are used to locate the start of the SPE in a
SONET frame. These two bytes contain the offset value, in bytes, between the pointer bytes and the start of
the SPE. These bytes are used for all the STS-1 signals contained in an STS-N signal to indicate the individ-
ual starting positions of the SPEs. They bytes also contain justication indications, concatenation indications
and path alarm indication (AIS-P).
– H3 - Pointer Action Byte (H3) - This byte is used during frequency justications. When a negative justication
is performed, one extra payload byte is inserted into the SONET frame. The H3 byte is used to hold this extra
byte and is hence called the pointer action byte. When justication is not being performed, this byte contains
a default value of 0x00.
– B2 - Line Bit-Interleaved Parity code (BIP-8) byte - This byte carries the parity information which is used to
check for transmission errors in a line. This is a even parity computed over all the bytes of the frame, except
section overhead bytes, before scrambling. The computed parity value is transmitted in the next frame in the
B2 position. This byte is dened for all the STS-1signals in an STS-N signal.
– K1, K2 - Automatic Protection Switching (APS channel) bytes - These bytes carry the APS information. They
are used for implementing automatic protection switching and for transmitting the line Alarm Indication Sig-
nal (AIS-L) and the Remote Defect Indication (RDI-L) signal.
– D4 to D12 - Line Data Communications Channel (DCC) bytes - These bytes provide a 576 Kbps channel for
transmission of information.
– S1- Synchronization Status - This byte carries the synchronization status of the network element. It is
located in the rst STS-1 of an STS-N. Bits 5 through 8 of this byte carry the synchronization status.
– Z1 - Growth - This byte is located in the second through Nth STS-1s of an STS-N and are allocated for future
growth. An STS-1 signal does not contain a Z1 byte.
– M0 - STS-1 REI-L - This byte is dened only for STS-1 signals and is used to convey the Line Remote Error
Indication (REI-L). The REI-L is the count of the number of B2 parity errors detected by an LTE and is trans-
mitted to its peer LTE as feedback information. Bits 5 through 8 of this byte are used for this function.
– E2 - Orderwire byte - This byte carries for line orderwire information.
SONET Mode Transmit Path
The transmit block performs the following functions in SONET mode:
A1 and A2 insertion and optional corruption
BIP-8 parity calculation, B1 byte insertion and optional corruption. (B1 byte is inverted.)
Performs RDI insertion (K2 byte is set to “0000 0110”).
Scrambling of outgoing data with optional scrambler disabling.
In either STS-192 or STS-48 mode, each link operates at an STS-48 rate.
TX Frame Processor
The Tx_Frame_Processor (TFP) block is the primary data processing block in the both SONET mode and cell
mode. It organizes the cell data into a SONET frame before sending it to the SERDES. The TFP is on the TSY-
CLKxx clock domain (77.76 MHz). In SONET mode, the 32-bit data comes from the FPGA interface. (In cell mode
the data comes from the cell processing block as described in the cell mode section) The TFP block contains three
major sub-blocks: payload block, TOH block and scrambler block. The interfaces for the TFP block are shown in
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORSO82G5 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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