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参数资料
型号： ORSO42G5-EV
厂商： Lattice Semiconductor Corporation
文件页数： 148/153页
文件大小： 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
标准包装： 1
系列： ORCA® 4 系列
类型： FPGA
适用于相关产品： ORSO42G5
所含物品： 板，线缆，电源
其它名称： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
94
Table 33. SERDES Per-Block Control Register Descriptions – ORSO82G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Per-Block Control Register (Read/Write) xx = [AA,...,BD]
30005 - A
30105 - B
[0]
RSVD
44
Reserved
—
[1]
GMASK_[A:B]
Global Mask. When GMASK_[A:B] = 1, the
transmit and receive alarms of all channel in
the SERDES block are prevented from gener-
ating an alarm (i.e., they are masked or dis-
abled). The GMASK_[A:B] bit overrides the
individual MASK_xx bits. GMASK_[A:B] = 1
on device reset.
Both
[2]
GSWRST_[A:B]
Software reset bit. The GSWRST_[A:B] bit
provides the same function as the hardware
reset for the transmit and receive sections of
all four channels, except that the device con-
guration settings are not affected when
GSWRST_[A:B] is asserted. This is not a self-
clearing bit. Once set, this bit must be manu-
ally set and cleared. The GSWRST_[A:B] bit
overrides the individual SWRST_xx bits.
GSWRST_[A:B] = 0 on device reset.
Both
[3]
GPWRDNT_[A:B]
Powerdown Transmit Function. When
GPWRDNT_[A:B] = 1, sections of the transmit
hardware for all four channels are powered
down. The GPWRDNT_[A:B] bit overrides the
individual PWRDNT_xx bits.
GPWRDNT_[A:B] = 0 on device reset.
Both
[4]
GPWRDNR_[A:B]
Powerdown Receive Function. When
GPWRDNR_[A:B] = 1, sections of the receive
hardware for all four channels are powered
down. The GPWRDNR_[A:B] bit overrides the
individual PWRDNR_xx bits.
GPWRDNR_[A:B] = 0 on device reset.
Both
[5:6]
RSVD
Reserved
—
[7]
GTESTEN_[A:B]
Global Test Enable Bit. When
GTESTEN_[A:B] = 1, the transmit and receive
sections of all channels in the block are place
in test mode. The TESTMODE_xx bits
(30006, 30106, etc.) must be set to specify
the desired test on a per-channel basis. The
GTESTEN_[A:B] bits override the individual
TESTEN_xx settings.
Factory
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相关代理商/技术参数
参数描述
ORSO82G5 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
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ORSO82G5-1BM680I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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