参数资料
型号: ORSO42G5-EV
厂商: Lattice Semiconductor Corporation
文件页数: 73/153页
文件大小: 0K
描述: BOARD EVAL DEV PLATFORM ORSO42G5
标准包装: 1
系列: ORCA® 4 系列
类型: FPGA
适用于相关产品: ORSO42G5
所含物品: 板,线缆,电源
其它名称: ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
26
Supported Data Formats
The ORSO42G5 and ORSO82G5 in the SONET mode support the following formats:
Single OC-48 on each of the channels at a bit rate of 2.488 Gbps.
OC-192 received in block OC-48 format on four channels at a combined rate of 9.952 Gbps.
The ORSO42G5 and ORSO82G5 SERDES will operate at the OC-12 rate of 622 MHz. For this rate, REFCLK is
set to 77 MHz and the SERDES is used in half rate mode. However the embedded core SONET framing/process-
ing logic is xed at the OC-48 rate and therefore can not talk directly with standard STS-12 devices. In order to
interoperate with standard STS-12 devices, the user must bypass the SONET functionality in the ORSO embedded
core (SERDES-only mode) and implement all framing, TOH and scrambling/descrambling functionality in FPGA
logic.
Figure 13 reveals the byte-ordering of the individual STS-48 streams. STS-192 is supported but it must be received
in the block STS-48 format as shown in Figure 14. Each OC-48 stream is composed of byte-interleaved OC-1 data
as described in GR-253 standard. Note that the SPE data is not touched by the core.
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