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| 型号： | ORSO42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 118/153页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL DEV PLATFORM ORSO42G5 |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORSO42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORSO42G5EV |
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Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
67
Reference Clock Requirements
There are two pairs of reference clock inputs in the ORSO42G5 and ORSO82G5 devices. Each reference clock is
distributed to all channels in a block. Each channel has a differential buffer to isolate the clock from the other chan-
nels. The input clock is preferably a differential signal; however, the device can operate with a single-ended input.
The input reference clock directly impacts the transmit data eye, so the clock should have low jitter. In particular, jit-
ter components in the DC to 5 MHz range should be minimized. The required electrical characteristics for the refer-
ence clock are given in Table 46.
Synthesized and Recovered Clocks
The SERDES Embedded Core block contains its own dedicated PLLs for transmit and receive clock generation.
The user provides a reference clock of the appropriate frequency, as described in the previous section. The trans-
mitter PLL uses the REFCLK_[A,B] inputs to synthesize the internal high-speed serial bit clocks. The receiver PLLs
extract the clock from the serial input data and retime the data with the recovered clock.
The receive PLL for each channel has two modes of operation - lock to reference and lock to data with retiming.
When no data or invalid data is present on the HDINP_xx and HDINN_xx pins, the receive VCO will not lock to data
and its frequency can drift outside of the nominal ±100 ppm range. Under this condition, the receive PLL will lock to
REFCLK_[A,B] for a xed time interval and then will attempt to lock to receive data. The process of attempting to
lock to data, then locking to clock will repeat until valid input data exists. There is also a control register bit per
channel to force the receive PLL to always lock to the reference clock.
The high-speed transmit and receive serial data links can run at 0.6 to 2.7 Gbps, depending on the frequency of the
reference clock and the state of the control bits from the internal transmit control register. The interface to the seri-
alizer/deserializer block runs at 1/8th the bit rate of the data lane. Additionally, the MUX/DEMUX logic converts the
data rate and bit-width so the FPGA core can run at 1/4th this frequency which gives a range of 18.8 to 84.4 MHz
for the data in and out of the FPGA in SONET mode. In cell mode, there is a clock domain transfer to a 2x clock
domain, which gives a range of 37.5 to 168.8 MHz for the data in and out of the FPGA.
Internal Clock Signals at the FPGA/Core Interface
There are several clock signals dened at the FPGA/Embedded Core interface in addition to the external reference
clock for each SERDES block. All of the ORSO42G5 and ORSO82G5 clock signals are shown in Figure 47 and are
described following the gure.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ORSO82G5 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
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