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参数资料
型号： ORSO42G5-EV
厂商： Lattice Semiconductor Corporation
文件页数： 146/153页
文件大小： 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
标准包装： 1
系列： ORCA® 4 系列
类型： FPGA
适用于相关产品： ORSO42G5
所含物品： 板，线缆，电源
其它名称： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
92
Table 29. SERDES Alarm and Alarm Mask Register Descriptions – ORSO82G5
Table 30. SERDES Per-Channel Transmit Conguration Register Descriptions – ORSO82G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Alarm Registers (Read Only) xx = [AA,...,BD]
30000 - AA
30010 - AB
30020 - AC
30030 - AD
30100 - BA
30110 - BB
30120 - BC
30130 - BD
[0]
RSVD
00
Reserved - May be non-zero
—
[1]
LKI_xx
Receive PLL Lock Indication, Channel xx.
LKI_xx = 1 indicates the receive PLL is locked.
Note that the PLL can either lock to the incom-
ing data or to RECLK_[A:B]. If the PLL is locked
to data and the data stream is terminated,
LKI_xx will go low until the PLL locks to
REFCLK_[A:B].
Both
[2:7]
RSVD
Reserved - May be non-zero
—
SERDES Alarm Mask Registers (Read/Write) xx = [AA,...,BD]
30001 - AA
30011 - AB
30021 - AC
30031 - AD
30101 - BA
30111 - BB
30121 - BC
30131 - BD
[0]
RSVD
FF
Reserved
—
[1]
MLKI_xx
Mask Receive PLL Lock Indication, Channel
MLKI_xx = 1 indicates LKI_xx is enabled
Both
[2:7]
RSVD
Reserved
—
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
SERDES Transmit Per-Channel Conguration Registers (Read/Write) xx = [AA,...,BD]
30002 - AA
30012 - AB
30022 - AC
30032 - AD
30102 - BA
30112 - BB
30122 - BC
30132 - BD
[0]
TXHR_xx
00
Transmit Half Rate Selection Bit, Channel xx.
When TXHR_xx = 1, HDOUT_xx's baud rate =
(REFCLK[A:B]*8) and TCK78[A:B] =(REF-
CLK[A:B]/4); when TXHR_xx=0, HDOUT_xx's
baud rate = (REFCLK[A:B]*16) and
TCK78[A:B]=(REFCLK[A:B]/2).
TXHR_xx = 0 on device reset.
Both
[1]
PWRDNT_xx
Transmit Powerdown Control Bit, Channel xx.
When PWRDNT_xx = 1, sections of the trans-
mit hardware are powered down.
PWRDNT_xx = 0 on device reset.
Both
[2]
PE0_xx
Transmit Preemphasis Selection Bit 0, Channel
xx. PE0_xx and PE1_xx select one of three pre-
emphasis settings for the transmit section.
PEO_xx=PE1_xx = 0, Preemphasis is 0%
PEO_xx=1, PE1_xx = 0 or PEO_xx=0,
PE1_xx = 1, Preemphasis is 12.5%
PEO_xx=PE1_xx = 1, Preemphasis is 25%.
PEO_xx=PE1_xx = 0 on device reset.
Both
[3]
PE1_xx
Both
[4]
HAMP_xx
Transmit Half Amplitude Selection Bit, Channel
xx. When HAMP_xx = 1, the transmit output
buffer voltage swing is limited to half its normal
amplitude. Otherwise, the transmit output buffer
maintains its full voltage swing.
HAMP_xx = 0 on device reset.
Both
[5:7]
RSVD
Reserved, Always set to “000”
—
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ORSO82G5-1F680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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