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参数资料
型号： ORSO42G5-EV
厂商： Lattice Semiconductor Corporation
文件页数： 81/153页
文件大小： 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
标准包装： 1
系列： ORCA® 4 系列
类型： FPGA
适用于相关产品： ORSO42G5
所含物品： 板，线缆，电源
其它名称： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
33
tee that this elastic store will not be overrun. The 32:8 MUX is also responsible for producing the divide-by-4 clock
from the SERDES output clock (XCK311) which is 311.04 MHz at a line rate of 2.488 Gbps.
SONET Mode Transmit Timing
Figure 17 shows the transmit clocks and a recommended clocking scheme. As shown, TCK78[A,B] can be used to
the source TSYSCLKxx signals. It is a requirement that TSYSCLKxx be frequency locked to the corresponding
TCK78[A,B] clock signal derived from REFCLK_[A:B].
Figure 17. Transmit Clocking Diagram in SONET Mode
When operating in SONET mode, the entire SONET frame is sent by the user. Optionally the TOH bytes can be
overwritten by the transmit block (AUTO_SOH or AUTO_TOH) before sending to scrambler and SERDES block.
Each SONET frame is 125 s given a 155.52MHz reference clock.
The frame starts with 36 clock cycles (77.76 MHz) of TOH followed by 1044 clock cycles of SPE, followed by
36 clock cycles of TOH, 1044 cycles of SPE etc. for all nine rows.
Figure 18. Transmit SONET Mode
SONET Mode Receive Path
The receiver block receives a byte from the SERDES blocks for each of the channels. The byte arrives at the
receiver block at 311.04 MHz. This data are not frame-aligned or word aligned. The data are rst passed through a
divide-by-4 DEMUX which produces a 32-bit word at 77.76 MHz. Data from the DEMUX is then passed through a
framer which aligns and frames the data. Data are processed based on cell mode or SONET mode.
In the SONET mode, the descrambled data are sent to an alignment FIFO that performs lane-to-lane deskew and
aligns data within an alignment group to the RSYCLK clock domain. Both the write and read clocks to the align-
xck311
LDIN[7:0]
32:8 MUX
32
FPGA
TCK78[A:B]
TOH Block
TSYSCLK xx
xx represents AC, AD, BC, BD (ORSO42G5) or AA, AB, AC, AD, BA, BB, BC, BD (ORSO82G5)
32
DINxx_FP
DINxx[31:0]
Scrambler
Logic Common to Each Block
TSYSCLKxx
DINxx[31:0]
DINxx_FP
T
TTT
T
S
T
S
TS
S
SS
S
T
...
1 cycle
36 cycles TOH
1044 cycles SPE
36 cycles TOH
Start of Frame
125 μs
Data
T Represents TOH
S Represents SPE
xx represents AC, AD, BC, BD (ORSO42G5) or
AA, AB, AC, AD, BA, BB, BC, BD (ORSO82G5).
36 cycles TOH
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相关代理商/技术参数
参数描述
ORSO82G5 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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