参数资料
型号: ORSO42G5-EV
厂商: Lattice Semiconductor Corporation
文件页数: 136/153页
文件大小: 0K
描述: BOARD EVAL DEV PLATFORM ORSO42G5
标准包装: 1
系列: ORCA® 4 系列
类型: FPGA
适用于相关产品: ORSO42G5
所含物品: 板,线缆,电源
其它名称: ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
83
30823 - AC
30833 - AD
30923 - BC
30933 - BD
[0]
BYPASS_ALGN_FIFO_xx
00
Bypass alignment FIFO =1 in RX path in
SONET mode. DOUT_xx data is clocked off
RWCKxx.
SONET
[1]
SERDES_ONLY_MODE_xx
SERDES-Only Mode. SERDES_ONLY_MODE
=1 bypasses all the SONET and cell functions.
Data is sent directly from the SERDES to the
FPGA logic in the RX path and is passed
directly from the FPGA logic to the SERDES in
the TX path.
SERDES
Only
[2]
FORCE_B1_ERR_xx
Force B1 Error. FORCE_B1_ERR =1 forces a
Section B1 error (Bit Interleaved Parity Error) in
the TX path. Valid only when the corresponding
AUTO_TOH_xx bit or AUTO_B1_xx bit is set to
one.
Both
[3]
FORCE_BIP8_ERR_xx
Force BIP8 Error, FORCE_BIP8_ERR =1 forces
cell BIP8 error in the TX path.
Cell
[4]
FORCE_A1A2_ERR_xx
Force A1A2 Error, FORCE_A1A2_ERR =1
forces an error in A1A2 bytes (framing error) in
the TX path. Valid only when the corresponding
AUTO_TOH_xx bit or AUTO_A1A2_xx bit is set
to one.
Both
[5]
FORCE_EX_SEQ_ERR_xx
Force Excessive Sequence Errors.
FORCE_EXP_SEQ_ERR_xx = 1 forces
sequence errors in the TX path by inverting the
link header byte sequence number.
Cell
[6]
FORCE_SEQ_ERR_xx
Force Sequence Error, FORCE_SEQ_ERR =1
forces one sequence error in the TX path. After
this bit is set, the next Link Header byte’s
sequence number is inverted. The Link Header
after the errored Link Header byte will have the
correct sequence number
Cell
[7]
FORCE_RDI_xx
Force Remote Defect Indication, FORCE_RDI
=1 forces RDI errors in the TX path. The K2 byte
in TOH is set to “00000110. Valid only when
AUTO_TOH_xx bit is set to 1.
Cell
Table 26. Per-Channel Control Register Descriptions – ORSO42G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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