参数资料
型号: ORSO42G5-EV
厂商: Lattice Semiconductor Corporation
文件页数: 152/153页
文件大小: 0K
描述: BOARD EVAL DEV PLATFORM ORSO42G5
标准包装: 1
系列: ORCA® 4 系列
类型: FPGA
适用于相关产品: ORSO42G5
所含物品: 板,线缆,电源
其它名称: ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
98
30806 - AA
30816 - AB
30826 - AC
30836 - AD
30906 - BA
30916 - BB
30926 - BC
30936 - BD
[0:5]
RSVD
00
Reserved
[6]
AUTO_B1_xx
AUTO_B1_xx = 0, B1 is not inserted by the
embedded core
AUTO_B1_xx = 1, B1 is calculated and inserted
by the embedded core
AUTO_TOH_xx = 1 overrides this bit
Both
[7]
AUTO_A1A2_xx
AUTO_A1A2_xx = 0, A1/A2 bytes are not
inserted by the embedded core
AUTO_A1A2_xx = 1, A1/A2 bytes inserted by
the embedded core
AUTO_TOH_xx = 1 overrides this bit
Table 35. Per-Channel Status Register Descriptions – ORSO82G5
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
Channel Status Registers (Read Only) xx = [AA,...,BD]
30808 - AA
30818 - AB
30828 - AC
30838 - AD
30908 - BA
30918 - BB
30928 - BC
30938 - BD
[0:4]
RSVD
00
Reserved
[5]
CELL_ALIGN_ERR_xx
Cell Alignment Error, CELL_ALIGN_ERR = 1
indicates that the internal transmit frame pro-
cessor did not detect a start of cell indicator
when it was expecting a new cell. If the corre-
sponding alarm enable bit has been set, a 1 on
this bit will cause an alarm.
Cell
[6]
TX_URUN_ERR_xx
Transmit Underrun Error, TX_URUN_ERR = 1
indicates an underrun error in the transmit
Asynchronous FIFO. If the corresponding alarm
enable bit has been set, a 1 on this bit will cause
an alarm.
Cell
[7]
TX_ORUN_ERR_xx
Transmit Overrun Error, TX_ORUN_ERR = 1
indicates an overrun error in the transmit Asyn-
chronous FIFO. The TX FIFO is designed to not
overow since it sends backpressure signal to
the FPGA when it cannot accept more cells. If
the corresponding alarm enable bit has been
set, a 1 on this bit will cause an alarm.
Cell
Table 34. Per-Channel Control Register Descriptions – ORSO82G5 (Continued)
(0x)
Absolute
Address
Bit
Name
Reset
Value
(0x)
Description
Mode
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