- 您现在的位置：买卖IC网 > PDF目录17102 > ORSO42G5-EV (Lattice Semiconductor Corporation)BOARD EVAL DEV PLATFORM ORSO42G5 PDF资料下载
参数资料
| 型号： | ORSO42G5-EV |
| 厂商： | Lattice Semiconductor Corporation |
| 文件页数： | 107/153页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL DEV PLATFORM ORSO42G5 |
| 标准包装： | 1 |
| 系列： | ORCA® 4 系列 |
| 类型： | FPGA |
| 适用于相关产品： | ORSO42G5 |
| 所含物品： | 板，线缆，电源 |
| 其它名称： | ORSO42G5EV |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页当前第107页第108页第109页第110页第111页第112页第113页第114页第115页第116页第117页第118页第119页第120页第121页第122页第123页第124页第125页第126页第127页第128页第129页第130页第131页第132页第133页第134页第135页第136页第137页第138页第139页第140页第141页第142页第143页第144页第145页第146页第147页第148页第149页第150页第151页第152页第153页
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
57
Link Header Detector
The Link Header detector determines when the next Link Header is coming in the frame and what the sequence
number contained within it should be. If the value of the cell sequence counter is not equal to the expected value,
then an error ag bit will set in the status registers and an error signal will be sent to the FPGA logic. The sequence
counter will increment to the next sequence number. The sequence count value is NOT updated with the incorrect
value, but is incremented each time a Link Header is received.
If excessive sequence errors are detected (three or more in a row), and the AUTO_REMOVE_[A:B] register bit is
set, then the corresponding link will be treated as not valid. The RX_LINK_GOOD status bit will go low indicating
the link is no longer receiving cells. If the AUTO_REMOVE_[A:B] register bit is not set, then the link is still valid
when excessive sequence errors are detected. An OOF condition will also trigger the link to be removed from ser-
vice if the AUTO_REMOVE_[A:B] register bit is set.
At startup or after a link has been removed from service (indicated by RX_LINK_GOOD going low), a link can be
rejoined into the group. This is performed via the per block REJOIN_[A:B] register bit. When rejoining a link the RX
FIFO will begin receiving cells. To cleanly rejoin a link into a group there are two methods to insure the RX FIFO
begins loading correctly. The rst method is to use the fast framing mode during the rejoin process. The can be
done by setting the FFRM_EN_xx for the links that need to be rejoined before setting the REJOIN_[A:B] bit.
The second method is to issue a block reset to clear the FIFO once all links that have been selected to be rejoined
are rejoined. This is done by rst setting the REJOIN_[A:B] bit. Once the RX_LINK_GOOD status bit is high for the
selected channels the GSWRST_[A:B] for the block should be set and cleared to reset the block. This method will
disturb trafc on all links in the block during the GSWRST_[A:B] reset time.
Once all of the links in a group are rejoined and the trafc is again owing the REJOIN_[A:B] bit should be cleared.
If this bit is not cleared, a link may drop out using the AUTO_REMOVE mode and the channel may be rejoined
incorrectly, causing errors on the entire group.
Receive FIFO
The main clock domain transfer for the data path is handled by the receive FIFO. A 16 x 161 FIFO is used in cell
mode. The FIFO is implemented as a dual-port memory which will support simultaneous reads and writes. The
receive FIFO block is written to at 77.76 MHz and read at 156 MHz.
The receive FIFO can allow for inter-link skew of about 800 ns (16 x 160 = 2560 bits, 400 ps per bit gives 1024 ns).
The 160 LSBs in the memory are received data and the 161st bit indicates the start of a new cell. The FIFO write
control logic indicates to the IPC, the start of a new frame of data. This signal will only be active for the A1 word of
a frame.
Once frame synchronization has occurred and the IPC has responded with a FIFO enable signal, data will be writ-
ten into the memory. Only the payload (cells) is written to the FIFO. The TOH bytes are not written into the FIFO.
The cell octets immediately following the A1A2 bytes will be always written to the top of the FIFO.
Once a full cell has been written to the memory, the write control logic will send a control signal to the IPC8 or IPC2
block which will start the process of reading data from the FIFO. The IPC will read one whole cell at a time from
each of the 8 FIFO blocks, if congured for the eight-link cell mode (ORSO82G5 only) or from each of 2 FIFO
blocks if congured for the two-link cell mode.
A FIFO occupancy counter generates a RX_FIFO_OVRUN indication to the register interface if it detects a FIFO
overow condition. The cell mode allows for alignment of all eight-links or alignment of two-links. Thus there will be
two IPC blocks for two pairs of channels per block.
Input Port Controllers
The input port controllers (IPCs) are the block responsible for “directing trafc” for the receive trafc ow. The block
diagrams for the 2-link and 8-link IPCs are shown in Figure 44. They provide the following essential functions.
Determining when cell data can be read from the FIFOs of the individual links.
相关PDF资料 |
PDF描述 |
|---|---|
| EEM22DTAT-S189 | CONN EDGECARD 44POS R/A .156 SLD |
| ECC20DRES | CONN EDGECARD 40POS .100 EYELET |
| AT-S-26-4/4/W-25-R | MOD CORD STANDARD 4-4 WHITE 25' |
| EEC40DREI | CONN EDGECARD 80POS .100 EYELET |
| 0210490869 | CABLE JUMPER 1.25MM .203M 17POS |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ORSO82G5 | 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs |
| ORSO82G5-1BM680C | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1BM680I | 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1F680C | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
| ORSO82G5-1F680I | 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256 |
发布紧急采购，3分钟左右您将得到回复。