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参数资料
型号： ORSO42G5-EV
厂商： Lattice Semiconductor Corporation
文件页数： 123/153页
文件大小： 0K
描述： BOARD EVAL DEV PLATFORM ORSO42G5
标准包装： 1
系列： ORCA® 4 系列
类型： FPGA
适用于相关产品： ORSO42G5
所含物品： 板，线缆，电源
其它名称： ORSO42G5EV
Lattice Semiconductor
ORCA ORSO42G5 and ORSO82G5 Data Sheet
71
Toggle SOFT_RESET once all clocks have stabilized
– 30A06
01
– 30A06
00
Provide a rising edge on the DIXxx_START signal
2. SONET Mode Initialization – ORSO82G5
This sample initialization uses the alignment FIFO for 4 channel alignment and Auto_SOH mode
Set 4 Channel Alignment (per channel, all channels in block A)
– 30802, etc. 60
Set SERDES PLL to Lock to Data signal (per channel, all channels in block A)
– 30804, etc. 80
Set Auto_Soh Mode (per channel, all channels in block A)
– 30806, etc. 03
Set NO_TX_RDI_EXSEQ Global register (block A). This is required to stop cell mode blocks from sending RDI
due to no cells.
– 30A03
80
Toggle SOFT_RESET once all clocks have stabilized
– 30A06
01
– 30A06
00
3. SONET Alignment FIFO Resynchronization – ORSO82G5
If during operation a link goes OOF the alignment group will continue to run without the errored channel. To realign
this link with the rest of group once the OOF condition is cleared the group may need to be resynchronized. This
operation (for 4 channel alignment in block A) is shown below.
Toggle the FMPU_RESYNC4_4 register bit to reset the alignment FIFO group.
– 30A04
48
– 30A04
00
This sequence will stop trafc temporarily on all links in the alignment grouping.
4. Two-Link Cell Mode Initialization – ORSO82G5
This sample initialization uses 2-link cell mode on all links (A1, A2, B1, and B2). Auto_Bundle and Auto_Remove
are both used for these links. The GSWRST_[A:B] Rejoin method is used.
Set SERDES PLL to Lock to Data signal and Auto_TOH mode (per channel, all channels)
– 30804, etc. 82
Set Auto_Remove and Rejoin
– 30A03
1B
Set 2-link cell mode for all groups A1, A2, B1 and B2
– 30A05
1E
Toggle SOFT_RESET
– 30A06
01
– 30A06
00
Set the TX_CFG_DONE bit to indicate the transmitter is completely congured
– 30A07
01
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相关代理商/技术参数
参数描述
ORSO82G5 制造商:LATTICE 制造商全称:Lattice Semiconductor 功能描述:0.6 to 2.7 Gbps SONET Backplane Interface FPSCs
ORSO82G5-1BM680C 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1BM680I 功能描述:FPGA - 现场可编程门阵列 10368 LUT 372 I/O RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680C 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7GBITS/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
ORSO82G5-1F680I 功能描述:FPGA - 现场可编程门阵列 ORCA FPSC 2.7Gbits/s BP XCVR 643K RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 栅极数量: 逻辑块数量:943 内嵌式块RAM - EBR:1956 kbit 输入/输出端数量:128 最大工作频率:800 MHz 工作电源电压:1.1 V 最大工作温度:+ 70 C 安装风格:SMD/SMT 封装 / 箱体:FBGA-256
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