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参数资料
| 型号： | RPIXP2850BB |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356 |
| 封装： | 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356 |
| 文件页数： | 128/130页 |
| 文件大小： | 1782K |
| 代理商： | RPIXP2850BB |
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Intel IXP2800 and IXP2850 Network Processors
Electrical Specifications
Datasheet
97
4.3
LC Filter Network
Figure 10 shows an example of an LC filter design that can be used to derive the power for the
analog and DLL power supplies for the IXP2800/IXP2850. For L1, a 10-ohm ferrite bead with a
DCR of less than 0.1 ohms should be used. For C1, a 10 microfarad capacitor should be used and
each analog VCC pin should be de-coupled with a 0.1 microfarad and a 0.01 microfarad capacitor.
4.4
AC/DC Specifications
4.4.1
Clock Timing Specifications
The IXP2800/IXP2850 has a centralized clock generator that takes an external reference frequency
and multiplies it to a higher base frequency clock, using a PLL. The resulting clock frequency is
then divided down by a set of programmable divisors to provide clocks to the SRAM, DRAM, and
optionally, the Media and Switch Fabric (MSF) controllers. All of the DRAM controllers are
clocked at the same rate, and therefore derive their clocks from a single divisor. Each SRAM
controller has a divisor, enabling it to be clocked individually. The Intel XScale
core and
Microengines derive their clocks from fixed-divide ratios.
The MSF derives its clock from either the internal PLL or an external source, such as a MAC
device. The selection is based on a the SP_AD[6] strap pin. When the pin is high, the MSF uses an
internally-generated clock using the programmable divisor. When the pin is low, the MSF uses an
externally-received clock. Refer to Section 3.2.11, “Configuration Pins” on page 41 for additional
details. The PCI controller also uses external clocks.
An external oscillator (CLK_REF_CLK_H/L) generates the initial IXP2800/IXP2850 clock
frequency. The CLK_REF_CLK range is between 75 to 125 MHz. The multiplier, used to generate
the PLL output frequency, is selected from strap bits SP_AD[5:0], and is in the range from 16 to
48.
Figure 10. LC Filter Network
B0138-02
.01 F
0.1 F
.01 F
0.1 F
.01 F
0.1 F
L1 = 10
Ω
1.35V
1.3V
1.2V
C1 = 10 F
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RPIXP2855AA | 制造商:Intel 功能描述: |
| RPIXP2855AB SLA7V | 制造商:Intel 功能描述: |
| RPIXP2855ACR | 制造商:Intel 功能描述: |
| RPIXP2855AD S LA7S | 制造商:Intel 功能描述:DEVICE CON IXP2855AD 1.50G PBG |
| RPIXP2855AD 888562 | 制造商:Intel 功能描述:CPU - Central Processing Units IXP2855 Network Proc 1.5GHz FCPGA2-1356 |
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