Intel IXP2800 and IXP2850 Network Processors
Electrical Specifications
Datasheet
101
4.4.3
Maximum Clock Frequencies
The clock frequency for each interface is derived from an integer divide in the range of 3 to 15 of
the Microengine operating frequency. As such, a device running at 1.4 GHz cannot simultaneously
achieve the maximum operating frequency for all of the external interfaces.
Table 32 lists examples
of the maximum frequencies achievable, based on the Microengine clock frequency.
4.4.4
Clock DC Parameters
The following clock-related signals use LVTTL signaling levels as shown in
Table 33.
CLK_PHASE_REF
CLK_STOP
CLK_PLL_BYP
CLK_NRESET
CLK_NRESET_OUT
Table 32. Example Maximum Clock Frequencies1
1. All values are in MHz.
Device
REF_CLK
PLL
Multiplier
PLL Output
Microengine
QDR
RDR2
2. Actual internal frequency is the RDR frequency divided by 4.
MSF3
3. If internally derived from the PLL, the maximum frequency for an external source is listed in
Table 31.
RPIXP2800BC
RPIXP2850BC
81.25
16
1300
650
163
432/108
325
Divisors
4
6
2
RPIXP2800BB,
RPIXP2850BB
100
28
2800
1400
233
508/127
466
Divisors
6
11
3
RPIXP2800BB,
RPIXP2850BB
100
24
2400
1200
200
533/133
400
Divisors
6
9
3
RPIXP2800BB,
RPIXP2850BB
100
25
2500
1250
208
500/125
416
Divisors
6
10
3
RPIXP2800BA,
RPIXP2850BA
100
20
2000
1000
200
400/100
333
Divisors
5
10
3
Table 33. Clock Buffer DC Specifications (Sheet 1 of 2)
Parameter
Conditions
Symbol
Minimum
Maximum
Unit
Notes
1, 2
Input High (Logic 1)
Voltage
Vcc = 3.0 to 3.6 V
VIH
2.0
VDD + 0.3
V
Input Low (Logic 0)
Voltage
Vcc = 3.0 to 3.6 V
VIL
-0.3
0.8
V
Input Leakage
Current
0 V
≤ Vin ≤ VDD
ILI
-10.0
10.0
uA
Output Leakage
Current
Outputs disabled,
0 V
≤ Vin ≤ VDD
ILo
-10.0
10.0
uA