Intel IXP2800 and IXP2850 Network Processors
Signal Description
38
Datasheet
3.2.6
GPIO Signals
GPIO are general-purpose I/O signals. They can be used for slow speed, software-controlled I/O
such as LEDs and input switches. They are also three-stated during reset to bring configuration
information into the network processor; the information is latched at the deassertion of
CLK_NRESET. The GPIO signals use LVTTL signaling levels – see
Table 11.3.2.7
Serial Port Signals
The serial port is an RS-232 compatible UART used for debug and diagnostics. See
Table 12 for
the serial port signals.
3.2.8
Clock and Reset Signals
All Clock and Reset signals, except for CLK_REF_CLK_H and CLK_REF_CLK_L, use LVTTL
signaling levels.
Table 13 lists the clock and reset signals.
Table 11. GPIO Signals
Signal Name
I/O
Description
Number
GPIO(0)
GPIO(1)
GPIO(2)
GPIO(3)
GPIO(4)
GPIO(5)
GPIO(6)
GPIO(7)
I/O
General Purpose I/O.
8
Total
8
Table 12. Serial Port Signals
Signal Name
I/O
Description
Number
SR_RX
I
Receive data into the UART.
1
SR_TX
O
Transmit data from the UART.
1
Total
2
Table 13. Clock Signals (Sheet 1 of 2)
Signal Name
I/O
Description
Number
CLK_REF_CLK_H
CLK_REF_CLK_L
I
PLL Clock Reference (LVDS). The CLK_REF_CLK input
pair does not have active on-die termination. This input pair
must be terminated on the PCB with a 100-ohm resistor
between the CLK_REF_CLK_H and CLK_REF_CLK_L
pins.
2
CLK_PHASE_REF
O
Reference clock phase delay output. In test mode, this
output pin determines the REF_CLK_LVDS input buffer
delay. In normal operation, this pin outputs the
programmed DRAM_N clock frequency from the on-board
PLL divided by 2, which is then used as the reference clock
for the Direct Rambus Clock Generator (DRCG).
1
CLK_STOP
I
PLL Stop Test Mode. Tie to logical 0 in normal operation.
1