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参数资料
| 型号： | RPIXP2850BB |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356 |
| 封装： | 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356 |
| 文件页数： | 38/130页 |
| 文件大小： | 1782K |
| 代理商： | RPIXP2850BB |
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Intel IXP2800 and IXP2850 Network Processors
Functional Units
Datasheet
15
The MSF supports 16-bit DDR LVDS signaling for the SPI-4 data path channel, and can be
configured to support either LVTTL or LVDS signaling for the SPI-4 FIFO status channel. The
MSF supports 16-bit LVDS signaling for CSIX-L1 protocol and 4-bit LVDS signaling for the Flow
Control interface.
2.7.1
SPI-4.2
SPI-4.2 is an interface for packet and cell transfer between a physical layer (PHY) device and a link
layer device (network processor), for aggregate bandwidths of OC-192 ATM and Packet over
SONET/SDH (POS), as well as 10 Gb/s Ethernet applications.
The SPI-4.2 protocol transfers data in bursts of variable length. Associated with each burst is
information such as port number (for a multi-port device such as a 10 x 1 GbE), SOP, and EOP.
This information is collected by the MSF and passed to the Microengines.
There are two options that do not require an extra oscillator to provide a clock for the data that
moves between two network processors on the same line card:
In the first option, the MAC device creates an RD_CLK to the first network processor, as
shown in Figure 6. RCLK_REF loops back into TCLK_REF for network processor 1, and
TCLK_REF is used as the source of the TD_CLK to network processor 2.
In the second option, the TD_CLK from network processor 1 to network processor 2 can be
created using a divide of network processor 1’s internal fast clock. The multiplex that selects
between the two possible sources of TD_CLK is controlled by a bit in the MSF_Tx_Control
CSR.
The Optical Internetworking Forum (OIF) controls the SPI-4.2 Implementation Agreement
document (available at http://www.oiforum.com).
2.7.2
CSIX
CSIX-L1 (Common Switch Interface, Level 1) defines an interface between a Traffic Manager
(TM) and a Switch Fabric (SF) for ATM, IP, MPLS, Ethernet, and similar data communication
applications.
The Network Processor Forum (NPF) controls the CSIX-L1 specification (available at
http://www.npforum.org and www.csix.org).
Figure 6. SPI-4 Clock Configuration for Dual Network Processors
A9317-01
IXP2800 #1
MAC
RD CLK
RCLK REF
TCLK REF
TD CLK
IXP2800 #2
RD CLK
RCLK REF
TCLK REF
TD CLK
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RPIXP2855AA | 制造商:Intel 功能描述: |
| RPIXP2855AB SLA7V | 制造商:Intel 功能描述: |
| RPIXP2855ACR | 制造商:Intel 功能描述: |
| RPIXP2855AD S LA7S | 制造商:Intel 功能描述:DEVICE CON IXP2855AD 1.50G PBG |
| RPIXP2855AD 888562 | 制造商:Intel 功能描述:CPU - Central Processing Units IXP2855 Network Proc 1.5GHz FCPGA2-1356 |
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