Intel IXP2800 and IXP2850 Network Processors
Electrical Specifications
Datasheet
105
4.4.6
SRAM
This section contains AC and DC parameters for the QDR.
Table 40. 66 MHz PCI Signal Timing
Symbol
Parameter
Minimum
Maximum
Unit
Tval
CLK to signal valid delay, bused
signals1
1. Bused signals are AD, CBE_L, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, DEVSEL_L, and STOP_L.
16
ns
Tval
(point-to-point)
CLK to signal valid delay,
point-to-point signals2
2. Point-to-point signals are REQ_L and GNT_L.
16
ns
Ton
Float to active delay3
3. Not tested. Guaranteed by design.
2—
Toff
—6
ns
Tsu
Input setup time to CLK, bused
signals4
4. Bused signals are AD, CBE_L, PAR, PERR_L, SERR_L, FRAME_L, IRDY_L, TRDY_L, DEVSEL_L, and STOP_L.
3—
ns
Tsu
(point-to-point)
Input setup time to CLK,
point-to-point signals5
5. Point-to-point signals are REQ_L and GNT_L.
5—
ns
Th
Input signal hold time from CLK
0
—
ns
Table 41. QDR DC Specifications
Symbol
Parameter
Conditions
Minimum
Maximum
Unit
Notes
1,2,3,4
1. All voltages are referenced to VSS (GND).
2. Overshoot: VIH (AC)
≤ VDD + 0.7 V for t ≤ t3.0 ns.
3. Not tested. Design requirement validated by simulations.
4. HSTL outputs meet JEDEC HSTL Class I standard.
VIH
Input High Voltage
(Logic 1)
VREF + 0.1
VDDQ + 0.3
V
VIL
Input Low Voltage
(Logic 0)
-0.3
VREF - 0.1
V
VIN
Clock Input Signal
Voltage
-0.3
VDDQ + 0.3
V
ILI
Input Leakage
Current
0 V
≤ VIN ≤ VDDQ
-25
25
uA
ILO
Output Leakage
Current
Output(s) disabled,
0 V
≤ VIN ≤ VDDQ (Q)
-25
25
uA
VOH
Output High Voltage
|IOH|
≤ 0.1mA
VDDQ - 0.2
VDDQ
V
VOL
Output Low Voltage
IOL
≤ 0.1mA
VSS
0.2
V
VDD
Supply Voltage
1.25
1.45
V
VDDQ
Isolated Output Buffer
Supply
1.4
1.6
V
VREF
Reference Voltage
0.7
0.8
V