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| 型号： | RPIXP2850BB |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356 |
| 封装： | 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356 |
| 文件页数： | 130/130页 |
| 文件大小： | 1782K |
| 代理商： | RPIXP2850BB |
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Intel IXP2800 and IXP2850 Network Processors
Electrical Specifications
Datasheet
99
Table 30 shows the frequencies that are available for DRAM, SRAM, and MSF, based on various
values of the PLL output clock.
Table 28. REF_CLK DC Specifications
Symbol
Parameter
Minimum
Typical
Maximum
Unit
Notes
1, 2, 3 4, 5, 6,
7, 8
1. Not a functional spec. Reliability limit.
2. Crossing Voltage is defined as the absolute voltage where the rising edge of CLK_REF_CLK_H is equal to the falling edge of
CLK_REF_CLK_L. Guaranteed by design simulations.
3. As defined in IEEE 1596.3.
4. Guaranteed by design.
5. Overshoot is defined as the absolute value of the maximum voltage allowed.
6. Undershoot is defined as the absolute minimum voltage allowed.
7. Ringback margin is defined as the absolute voltage difference between the maximum rising edge ringback and the maximum
falling edge ringback.
8. Threshold region is defined as a region entered at the crossing voltage in which the differential receiver switches. It includes
input threshold hysteresis.
Vabsolute
Absolute Voltage
Range
– 0.3
—
VCC25 + 0.3
V
Vi
Input Common Mode
Voltage Range
825
—
1575
mV
VCROSS
Crossing Voltage
875
1200
1525
mV
VOV
Overshoot
N/A
VCC25 + 0.3
V
VUS
Undershoot
– 0.3
N/A
V
VRBM
Ringback Margin
0.200
N/A
V
VTH
Threshold Margin
VCROSS –
0.100
—
VCROSS +
0.100
V
Table 29. REF_CLK AC Specifications
Parameter
Minimum
Typical
Maximum
Unit
Notes
1,2,3,4,5,6
1. These specifications apply to CLK_REF_CLK.
2.
Guaranteed by design.
3. The period specified here is the average period. A given period may vary from this specification, as governed by the period
stability specification.
4. Rise/Fall time is measured between the 20% and 80% points of the clock swing.
5. Maximum combination of determinstic and random jitter components.
6. This parameter is not tested. It is guaranteed by design. Low cycle-to-cycle input jitter (<16ps) can be guaranteed by design
if all the following conditions are met: good board layout, good supply decoupling, <1” between resistor terminator and
IXP28XX, and a high-quality oscillator (such as an EPSON ultra-low jitter SAW oscillator). The use of translators is allowed,
but not recommended because additional jitter will be introduced. If any of these conditions are not met, the cycle-to-cycle jitter
must be measured in the system to confirm that max jitter spec is met.
Reference Clock Input Frequency
75
100
125 2
MHz
T1: CLK_REF_CLK_(L/H) Period
13.3
—
8
ns
CLK_REF_CLK Input Duty Cycle
40
50
60
%
T5: CLK_REF_CLK_(L/H) Rise Time
—
1
ns
T6: CLK_REF_CLK_(L/H) Fall Time
—
1
ns
PERIOD JITTER Peak-to-Peak
50 2
ps
JITTER Cycle-toCycle
16
ps
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相关代理商/技术参数 |
参数描述 |
|---|---|
| RPIXP2855AA | 制造商:Intel 功能描述: |
| RPIXP2855AB SLA7V | 制造商:Intel 功能描述: |
| RPIXP2855ACR | 制造商:Intel 功能描述: |
| RPIXP2855AD S LA7S | 制造商:Intel 功能描述:DEVICE CON IXP2855AD 1.50G PBG |
| RPIXP2855AD 888562 | 制造商:Intel 功能描述:CPU - Central Processing Units IXP2855 Network Proc 1.5GHz FCPGA2-1356 |
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