参数资料
型号: RPIXP2850BB
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356
封装: 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356
文件页数: 45/130页
文件大小: 1782K
代理商: RPIXP2850BB
Intel IXP2800 and IXP2850 Network Processors
Signal Description
Datasheet
21
3.2
Pin Description, Grouped by Function
This section provides an overview of the network processor I/O signals. Detailed definitions and
descriptions of signal usage can be found in sections specific to each interface.
The network processor signals are categorized into one of several groups, as shown in Table 4.
3.2.1
RDRAM
There are three channels of RDRAM. The I/O design supports long-channel and short-channel
board implementations. Long-channel is RIMM based, and short-channel is board-mounted. The
RDR channels support PC600, PC800, and 1066-MHz RDR parts. The RDR channels allow
programmatic selection of ECC. Long- and short-channel design guides are available from
Rambus*. The long-channel design supports one RIMM load.
There are three Rambus* DRAM (RDRAM) channels, and each channel has the signals shown in
Table 5. The DRAMs use RSL signaling levels, with the exception of SIO, CMD, SCK, PClkM,
and SynClkN, which are CMOS.
Table 4.
IO Signal Prefix Categories
IO Signal Group Prefix
Description
CLK
Clocks, reset, and test control signals related to the PLL clock
SP
Slowport
TEST
Test port
JTAG
Joint Test Action Group
GPIO
General purpose IO
SR
Serial port
SPI4
SPI-4
FC
Flow control
QDRn
Four QDR ports
RDRn
Three Rambus* ports
PCI
Table 5.
RDRAM Signals (Sheet 1 of 3)
Signal Name
I/O
Description
Number
RDR0_SIO
RDR1_SIO
RDR2_SIO
I/O
Serial Data
3
RDR0_CMD
RDR1_CMD
RDR2_CMD
O
Command
3
RDR0_SCK
RDR1_SCK
RDR2_SCK
O
Serial Clock
3
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