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参数资料
型号： RPIXP2850BB
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356
封装： 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356
文件页数： 98/130页
文件大小： 1782K
代理商： RPIXP2850BB
Intel IXP2800 and IXP2850 Network Processors
Product Description
Datasheet
7
1.0
Product Description
The Intel
IXP2800 and IXP2850 network processors are second-generation high-performance
network processors based on the first generation Intel
IXP1200 network processor design. They
are fully programmable network processors that implement a high-performance parallel processing
architecture on a single chip designed for processing complex algorithms, deep packet inspection,
traffic management, and forwarding at wire-speed. Its store-and-forward architecture combines a
high-performance Intel XScale
core with sixteen 32-bit independent multithreaded Microengines
that cumulatively provide more than 25 giga-operations per second. The Microengines provide the
processing power to perform dataplane tasks that traditionally required expensive high-speed
ASICs.
Intel’s second-generation network processors are the first implementation of Intel’s Hyper Task
Chaining technology. This unique network processing approach allows a single stream packet/cell
processing problem to be decomposed into multiple, sequential tasks that can be linked together
easily. The hardware design uses fast and flexible sharing of data and event signals among threads
and Microengines to manage data-dependent operations using multiple parallel processing stages,
with low latency. Through this combination of flexible software pipelining and fast inter-process
communication, Hyper Task Chaining delivers rich processing capability at OC-192/10 Gbps line
rates.
1.1
Hyper Task Chaining
Hyper Task Chaining implements several significant innovations to ensure low latency
communication among processes. These mechanisms include “Next Neighbor” registers that
enable individual Microengines to rapidly pass data and state information to adjacent
Microengines. Reflector Mode pathways ensure that data and global event signals can be shared
with multiple Microengines, using 32-bit unidirectional buses that connect the network processor’s
internal processing and memory resources. A third enhancement, Ring Buffer registers, provides a
highly efficient mechanism for flexibly linking tasks among multiple software pipelines.
Ring buffers allow developers to establish “producer-consumer” relationships among
Microengines, efficiently propagating results along the pipeline in FIFO order. To minimize
latency associated with external memory references, register structures are complemented by 16
entries of Content Addressable Memory (CAM) associated with each Microengine. Configured as
a distributed cache, the CAM enables multiple threads and Microengines to manipulate the same
data simultaneously, while maintaining data coherency.
Figure 1 is a block diagram of the IXP2800 network processor, and Figure 2 is a block diagram of
the IXP2850 network processor.
Figure 3 shows two IXP2800 network processors in a typical 10 Gb/s full duplex line card with a
switch fabric interface.
相关PDF资料
PDF描述
RPM-075PTT86 PHOTO TRANSISTOR DETECTOR
RS5C316B-E2 0 TIMER(S), REAL TIME CLOCK, PDSO8
RS5C317B-E1 0 TIMER(S), REAL TIME CLOCK, PDSO14
RS5C317B-E2 0 TIMER(S), REAL TIME CLOCK, PDSO14
RS5C321A-E1 0 TIMER(S), REAL TIME CLOCK, PDSO8
相关代理商/技术参数
参数描述
RPIXP2855AA 制造商:Intel 功能描述:
RPIXP2855AB SLA7V 制造商:Intel 功能描述:
RPIXP2855ACR 制造商:Intel 功能描述:
RPIXP2855AD S LA7S 制造商:Intel 功能描述:DEVICE CON IXP2855AD 1.50G PBG
RPIXP2855AD 888562 制造商:Intel 功能描述:CPU - Central Processing Units IXP2855 Network Proc 1.5GHz FCPGA2-1356
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