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参数资料
| 型号： | RPIXP2850BB |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356 |
| 封装： | 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356 |
| 文件页数： | 13/130页 |
| 文件大小： | 1782K |
| 代理商： | RPIXP2850BB |
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Intel IXP2800 and IXP2850 Network Processors
Functional Units
Datasheet
11
2.3
Microengines
The Microengines do most of the programmable per-packet processing in the network processor.
There are 16 Microengines, connected as shown in Figure 4. The Microengines can access all of
the shared resources (SRAM, DRAM, MSF, etc.) and the private connections between adjacent
Microengines.
The Microengines provide support for software-controlled multi-threaded operation. Given the
disparity in processor cycle times compared to external memory times, a single thread of execution
often blocks, waiting for external memory operations to complete. Multiple threads enable
interleave operations — there is usually at least one thread ready to run while others are waiting.
2.4
Cryptography Unit
The IXP2850 network processor has two cryptography units – Crypto 0 and Crypto 1
(see Figure 4) that perform bulk data encryption and authentication. The cryptography units
interface only to the Microengines and Media Switch Fabric, and contain input RAM available for
receiving input data from the Microengine and RBUF (receive buffer) elements. Both
cryptography units support the Data Encryption Standard (DES), Triple DES (3DES), and
Advanced Encryption Standard (AES) algorithms, and Secure Hash Algorithm (SHA-1) hashing.
Each cryptography unit has two 3DES cores, one AES core, and two SHA-1 cores:
Each 3DES core can access three encryption/decryption Key states and three Initialization
Vectors (IV).
The AES core can access six Key states and six IVs.
The 3DES and AES cores can be used with or without Cipher Block Chaining.
The AES cores support a block size of 128 bits, and Key lengths of 128, 192, and 256 bits.
The SHA-1 cores have hardware support to implement the Keyed-Hash Message
Authentication Code (HMAC) algorithm, with minimal Microengine intervention.
The cryptography units operate at half the Microengine frequency.
2.5
RDRAM
The IXP2800/IXP2850 has controllers for three Rambus* DRAM (RDRAM) channels. Each of the
controllers independently accesses its own RDRAMs, and can operate concurrently with the other
controllers (i.e., they are not operating as a single, wider memory). DRAM provides high density,
high bandwidth storage and is typically used for data buffers.
RDRAM sizes of 64, 128, 256, and 512 Mbytes, and 1 Gbyte are supported. However, each of the
channels must have the same number, size, and speed of RDRAMs populated. Each channel can be
populated with one to four per bank, for short-channel and one RIMM for long-channel.
Up to two Gbytes of DRAM is supported. If less than two Gbytes of memory is available, the upper
part of the address space is not used. It is also possible (for system cost and area savings) to have
Channels 0 and 1 populated with Channel 2 empty, or Channel 0 populated with Channels 1 and 2
empty.
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相关代理商/技术参数 |
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| RPIXP2855AA | 制造商:Intel 功能描述: |
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