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参数资料
| 型号： | RPIXP2850BB |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356 |
| 封装： | 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356 |
| 文件页数： | 64/130页 |
| 文件大小： | 1782K |
| 代理商： | RPIXP2850BB |
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Intel IXP2800 and IXP2850 Network Processors
Signal Description
Datasheet
39
3.2.9
Power Supply Pins
CLK_PLL_BYP
I
PLL Bypass Test Mode. When asserted, the
IXP2800/IXP2850 uses the external clock inputs
(CLK_REF_CLK in place of PLL clocks. This pin should be
tied to logical 0 during normal operation.
1
CLK_NRESET
I
Master Reset Input. Active low.
All configuration strap options are latched on the
deassertion of this signal. This signal must be toggled even
in PCI BOOT mode to latch the configuration straps
options.
1
CLK_NRESET_OUT
O
Reset Output. Active low. This output is controlled by
configuration pin SP_AD[7] listed in Table 16 Configuration
Pins.
1
Total
7
Table 14. Power Supply Pins (Sheet 1 of 2)
Signal Names
Total
Pin Descriptions
VCC_CLK
1
2.5 V supply. May be tied to the same board level supply as VCC25V.
VCC_FUSE
4
1.35/1.3/1.2 V supply for the fuse logic. May be tied to the same board level
supply as VCC. The fuse circuit supply has been isolated from VCC because
this supply must be elevated during the fuse programming sequence, which
only occurs during final manufacturing test (not user accessible).
VREFHI_CLK
1
These pins should be tied to VSS (logical 0).
VREFLO_CLK
1
These pins should be tied to VSS (logical 0).
VCC_PLL
1
1.35/1.3/1.2 V supply for the on-chip PLL. If the board level supply is
exceptionally clean, this supply could be tied to the same board level supply as
VCC. Given that most applications witness substantial noise on VCC, the
VCC_PLL should be generated by filtering VCC with an LC network
(see Figure 10).
VCC
78
Core power supply.
VSS
371
Core ground.
VCC25V
28
SPI-4 supply (also for PCI).
VCCA_FC
1
DLL power. Should be generated by filtering VCC with an LC network
(see Figure 10).
VCCA_SPI4
1
DLL power. Should be generated by filtering VCC with an LC network
(see Figure 10).
VREFHI
2
SPI-4/flow reference voltage.
VREFLO
2
SPI-4/flow reference voltage.
VCC33
4
GPIO, JTAG, SP power.
VCC33_PCI
12
PCI power supply.
VDDQ
101
QDR power supply.
PAS0_VCCA
1
DLL power. Should be generated by filtering VCC with an LC network
(see Figure 10).
Table 13. Clock Signals (Sheet 2 of 2)
Signal Name
I/O
Description
Number
相关PDF资料 |
PDF描述 |
|---|---|
| RPM-075PTT86 | PHOTO TRANSISTOR DETECTOR |
| RS5C316B-E2 | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| RS5C317B-E1 | 0 TIMER(S), REAL TIME CLOCK, PDSO14 |
| RS5C317B-E2 | 0 TIMER(S), REAL TIME CLOCK, PDSO14 |
| RS5C321A-E1 | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RPIXP2855AA | 制造商:Intel 功能描述: |
| RPIXP2855AB SLA7V | 制造商:Intel 功能描述: |
| RPIXP2855ACR | 制造商:Intel 功能描述: |
| RPIXP2855AD S LA7S | 制造商:Intel 功能描述:DEVICE CON IXP2855AD 1.50G PBG |
| RPIXP2855AD 888562 | 制造商:Intel 功能描述:CPU - Central Processing Units IXP2855 Network Proc 1.5GHz FCPGA2-1356 |
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