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| 型号： | RPIXP2850BB |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356 |
| 封装： | 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356 |
| 文件页数： | 24/130页 |
| 文件大小： | 1782K |
| 代理商： | RPIXP2850BB |
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Intel IXP2800 and IXP2850 Network Processors
Functional Units
12
Datasheet
Reads and writes to RDRAM are generated by Microengines, Intel XScale
core, and PCI
(external Bus Masters and DMA Channels). The controllers also do refresh and calibration cycles
to the RDRAMs, transparently to software.
Note:
RDRAM Powerdown and Nap modes are not supported.
Hardware interleaving of addresses (also called striping) provides balanced access to all populated
channels; the interleave size is 128 bytes. Interleaving helps to maintain utilization of available
bandwidth by spreading consecutive accesses to multiple channels. The interleaving is done in the
hardware so that the three channels appear to software as a single contiguous memory space.
ECC (Error Correcting Code) is supported, but can be disabled. Enabling ECC requires that x18
RDRAMs be used; if ECC is disabled, x16 RDRAMs can be used. ECC can detect and correct all
single-bit errors, and detect all double-bit errors. When ECC is enabled, partial writes (writes of
less than eight bytes) must be done as read-modify-writes.
2.6
SRAM
The network processor has four independent SRAM controllers, each of which supports pipelined
QDR synchronous static RAM (SRAM) and/or a coprocessor that adheres to QDR signaling. Any
or all controllers can be left unpopulated if the application does not need to use them. SRAM is
accessible by the Microengines, the Intel XScale
core, and the PCI Unit (external bus masters and
DMA).
The memory is logically four bytes (32-bits) wide; physically, the data pins are two bytes wide and
are double-clocked. Byte parity is supported, and each of the four bytes has a parity bit, which is
written when the byte is written and checked when the data is read. There are byte enables that
select the bytes to be written, for writes of less than 32-bits.
Each of the four QDR ports are QDR- and QDRII-compatible; each port implements the “_K” and
“_C” output clocks and “_CIN” as an input and their inversions. (Note: the “_C” and “_CIN”
clocks are optional). Extensive work has been done to provide impedance controls within the
IXP2800/IXP2850 for IXP2800/IXP2850-initiated signals driving to QDR parts. Providing a clean
signaling environment is critical to achieving 200- to 233-MHz QDRII data transfers.
The configuration assumptions for the network processor I/O driver/receiver development includes
four QDR loads and the network processor. The network processor supports bursts of two SRAMs
(bursts of four SRAMs are not supported).
The SRAM controller can also be configured to interface to an external coprocessor that adheres to
the QDR electricals and protocol. Each SRAM controller can also interface to an external
coprocessor through its standard QDR interface. This interface enables both SRAM devices and
coprocessors to operate on the same bus. The coprocessor behaves as a memory-mapped device on
the SRAM bus.
2.6.1
QDR Clocking Scheme
The controller drives out two pairs of K clock (K and K#), and two pairs of C clock (C and C#).
Both C/C# clocks externally return to the controller for reading data. Figure 5 shows the clock
diagram of the clocking scheme for a QDR interface driving four SRAM chips.
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相关代理商/技术参数 |
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