参数资料
型号: RPIXP2850BB
厂商: INTEL CORP
元件分类: 微控制器/微处理器
英文描述: 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356
封装: 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356
文件页数: 29/130页
文件大小: 1782K
代理商: RPIXP2850BB
Intel IXP2800 and IXP2850 Network Processors
Electrical Specifications
124
Datasheet
When the system is powered up, the bypass clock is sent to all of the units as the chip begins to
power up. It will be used to allow a gradual power-up and to begin clocking state elements to
remove possible circuit contention. When the PLL gets locked after CLK_NRESET is de-asserted,
it will start generating “divide-by-16” clocks for all of the units. A reset from the CLK_NRESET
register is also removed at the same time.
The reset sequence shown above is the same in the case when reset happens through the PCI_RST#
signal and CFG_RST_DIR is asserted.
4.4.15
Serial Port
The serial port consists of TXD and RXD, which are asynchronous relative to any device outside of
the network processor. The serial port IO buffer DC specifications are the same as the GPIO IO DC
buffer specifications.
2. This parameter is applicable to all of the configuration pins listed in Section 3.2.11.
3. REF_CLK can be in the range of 75 - 125 MHz, as specified in Table 29 REF_CLK AC Specifications.
Figure 27. Reset Timing
B2668-02
Configuration
Strap Pins
CLK_
NRESET
REF
_CLK
VDD
tSS
tRST
REF_CLK
and VDD stable
RESET#
de-assertion
tHS
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