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参数资料
型号： RPIXP2850BB
厂商： INTEL CORP
元件分类： 微控制器/微处理器
英文描述： 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356
封装： 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356
文件页数： 23/130页
文件大小： 1782K
代理商： RPIXP2850BB
Intel IXP2800 and IXP2850 Network Processors
Electrical Specifications
Datasheet
119
4.4.12
GPIO
The GPIO can be used with appropriate software in I
2C applications. Refer to Philips
Semiconductors* I
2C bus specification for the DC and AC characteristics. Table 61 shows the DC
characteristics for a fast mode I
2C bus device. It can also be used for test purposes.
Table 60. Slowport Read AC Parameters1
External Signals
tco2 l
max/min (ns)
th3 (ns)
min
tsu (ns)
min
tpw
(ns)
toz/zo
max/min (ns)
loading
(pF)
SP_ALE
9.0/1.5
50
SP_CS[0]
9.0/1.5
50
SP_CS[1]
9.0/1.5
50
SP_RD
9.0/1.5
50
SP_ACK
1.0
12.2
SP_AD[1:0]
9.0/1.5
50
SP_AD[7:0]
output to external device
9.0/1.5
12.2/1.0
SP_AD[7:0]
input from external device
1.0
12.2
1. These timing parameters are specified for a 1.4 GHz core frequency and from the rising edge of SP_CLK. Guaranteed by
functional tests.
2. The default output timing is controlled by the TXE register; refer to the Intel IXP2400 and IXP2800 Programmer’s Reference
Manual for further details. By default, this register is set to a value of 0x1. For each increment to this register, a PCLK period
delay is added to both the maximum and minimum specified values. For example, for a PCLK frequency of 700 MHz, a period
delay is ~ 1.4 ns; using a TXE register value of 0x5, the maximum and minimum delay values would be calculated as follows:
Max = 9.0 + (5- 1) * 1.4 = 14.6 ns.
Min = 1.5 + (5 - 1) * 1.4 = 7.1 ns.
Note: this delay should not exceed the cycle time of SP_CLK.
3. The sampling of the SP_ACK_L and SP_AD signals is controlled by the RXE register. Refer to the Intel IXP2400 and
IXP2800 Programmer’s Reference Manual for further details. By default, this register is set to a value of 0x1. For each incre-
ment to this register, a PCLK period delay is added to the setup and is subtracted from the hold specified values. For exam-
ple, for a PCLK frequency of 700 MHz, a period delay is ~ 1.4 ns; using an RXE register value of 0x5, the setup and hold
delay values would be calculated as follows:
Setup = 12.2 + (5-1) * 1.4 = 17.8 ns.
Hold = 1.0 - (5-1) * 1.4 = - 4.6 ns.
Note: this delay should not exceed the cycle time of SP_CLK.
Table 61. GPIO I/O Buffer DC Specifications
Parameter
Conditions
Symbol
Minimum
Maximum
Unit
Notes
1, 2
Input High (Logic 1)
Voltage
VIH
2.0
VDD + 0.3
V
1
Input Low (Logic 0)
Voltage
VIL
-0.3
0.8
V
1
Input Leakage
Current
0 V
≤ Vin ≤ VDD
ILI
-10.0
10.0
uA
Output Leakage
Current
Outputs disabled,
0 V
≤ Vin ≤ VDD
ILo
-10.0
10.0
uA
Output High Voltage
IOH = -4.0 mA
VOH
2.4
-
V
1, 2
Output Low Voltage
IOL = 4.0 mA
VOL
-
0.4
V
1, 2
Supply Voltage
VDD
3.1
3.5
V
1
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