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参数资料
| 型号： | RPIXP2850BB |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 1400 MHz, RISC PROCESSOR, PBGA1356 |
| 封装： | 37.50 X 37.50 MM, 1 MM PITCH, FCBGA-1356 |
| 文件页数： | 67/130页 |
| 文件大小： | 1782K |
| 代理商： | RPIXP2850BB |
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Intel IXP2800 and IXP2850 Network Processors
Signal Description
Datasheet
41
3.2.11
Configuration Pins
These pins are tied statically high or low through a resistor to provide configuration information
into the network processor at reset. For all but CFG_RST_DIR, these pins are used for other
purposes after reset. For those pins, the configuration information is sampled at the deassertion
(rising) edge of CLK_NRESET. The values sampled can be read in the Strap_Options register.
JTAG_TRST
I
Test interface reset. When asserted low, the TAP controller
is asynchronously forced to enter a reset state, which in
turn asynchronously initializes other test logic. This pin
must be driven or held low to achieve normal device
operation.
1
TEST_SCAN_CLK_A
TEST_SCAN_CLK_B
I
Scan Chain Clocks. These pins are used to input the scan
clocks used during scan testing and must be tied to a
logical 1 in a system environment.
2
TEST_SCAN_EN
I
Scan Chain Enable. This input pin places the chip in scan
test mode when asserted, and is only used during scan
testing. This pin should be tied to a logical 0 in a system
environment.
1
TEST_SCAN_MODE
I
Strobe Test Mode Pins. This input pin is used to latch
values into the Test Mode Register and is used in
conjunction with INTERRUPT_MODE, SP_AD[7:0] and
GPIO[3:0] during scan testing. This pin should be tied to a
logical 0 in a system environment.
Note: For the A stepping of the device, the name of this pin
was TEST_CLK. The name was changed in the B
stepping; however, the functionality of the pin is identical.
1
TEST_DIODE_A
I
Thermal Diode Anode. This pin should be tied to a logical 0
if the pin is not being used.
1
INTERRUPT_MODE
I
1—Selects signals from the GPIO and Slowport pins to be
routed to the Test Box instead of the GPIO and Slowport
ports, and sets the JTAG_TMS, TEST_SCAN_MODE,
JTAG_TDI, and TEST_SCAN_EN pins to operate in their
test mode.
0—These pins have their normal function.
This pin should be tied to a logical 0 in a system
environment.
Note: For the A stepping of the device, the name of this pin
was TEST_MODE_LOAD. The name was changed in the
B stepping; however, the functionality of the pin is identical.
1
TEST_DIODE_C
I
Thermal Diode Cathode. This pin should be tied to a logical
0 if the pin is not being used.
1
CLK_RST_DIS
I
This is a test mode control input to the IXP2800/IXP2850
and is only used during scan testing. This signal must be
tied to a logical 0 in a system environment.
Total
12
Table 15. Test and JTAG Signals (Sheet 2 of 2)
Signal Name
I/O
Description
Number
相关PDF资料 |
PDF描述 |
|---|---|
| RPM-075PTT86 | PHOTO TRANSISTOR DETECTOR |
| RS5C316B-E2 | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
| RS5C317B-E1 | 0 TIMER(S), REAL TIME CLOCK, PDSO14 |
| RS5C317B-E2 | 0 TIMER(S), REAL TIME CLOCK, PDSO14 |
| RS5C321A-E1 | 0 TIMER(S), REAL TIME CLOCK, PDSO8 |
相关代理商/技术参数 |
参数描述 |
|---|---|
| RPIXP2855AA | 制造商:Intel 功能描述: |
| RPIXP2855AB SLA7V | 制造商:Intel 功能描述: |
| RPIXP2855ACR | 制造商:Intel 功能描述: |
| RPIXP2855AD S LA7S | 制造商:Intel 功能描述:DEVICE CON IXP2855AD 1.50G PBG |
| RPIXP2855AD 888562 | 制造商:Intel 功能描述:CPU - Central Processing Units IXP2855 Network Proc 1.5GHz FCPGA2-1356 |
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