Intel IXP2800 and IXP2850 Network Processors
Electrical Specifications
102
Datasheet
4.4.5
PCI I/O Unit
This section specifies the following electrical behavior for the PCI I/O unit.
DC specifications
AC timing specifications
4.4.5.1
PCI DC Specifications
Note:
In
Table 34, currents into the chip (chip sinking) are denoted as positive (+) current. Currents from
the chip (chip sourcing) are denoted as negative (-) current. Input leakage currents include high-Z
output leakage for all bidirectional buffers with three-state outputs. The electrical specifications are
preliminary and subject to change.
4.4.5.2
PCI Overshoot/Undershoot Specifications
The PCI I/Os are designed to be tolerant of overshoot and undershoot associated with normal I/O
switching. However, excessive overshoot or undershoot of I/O signals can cause the device to latch
up. Table 35 specifies limits on I/O overshoot and undershoot that should never be exceeded.
Table 36 lists the maximum PCI Interface loading.
Output High Voltage
IOH = -4.0 mA
VOH
2.4
N/A
V
Output Low Voltage
IOL = 4.0 mA
VOL
N/A
0.4
V
Supply Voltage
VDD
3.1
3.5
V
1. All voltages referenced to Vss (GND).
2. The load used for VOH and VOL testing is shown in
Figure 22. AC load current is higher than the shown DC values.
Table 33. Clock Buffer DC Specifications (Sheet 2 of 2)
Parameter
Conditions
Symbol
Minimum
Maximum
Unit
Notes
1, 2
Table 34. PCI DC Specifications
Symbol
Parameter
Condition
Minimum
Maximum
Vih
Input High Voltage
0.5 x Vcc33
Vcc33 + 0.5 V
Vil
Input Low Voltage
—
0.3 x Vcc33
Voh
Output High Voltage
Ioh = -500 uA
0.9 x Vcc33
—
Vol
Output Low Voltage
Iol = 1500 uA
—
0.1 x Vcc33
Ii
Input Leakage Current1
1. Input leakage currents include high-impedance output leakage for all bidirectional buffers with three-state outputs.
0
≤ Vin ≤ Vcc33
-10 uA
10 uA
Cin
Pin Capacitance
5 pF
10 pF
Table 35. Overshoot/Undershoot Specifications
Pin Type
Undershoot
Overshoot
Maximum Duration
Input
– 0.7 V 1
4 ns
Output
4 ns