Intel IXP2800 and IXP2850 Network Processors
Electrical Specifications
Datasheet
113
Table 52. Transmitter and Receiver AC Timing Parasitics
FIFO Status Channel
The following section describes AC timing parameters for a FIFO status channel implemented
using LVTTL I/O. As noted in
Table 53, the maximum clock frequency of the LVTTL FIFO Status
Channel must not exceed of the selected data path clock rate. For an optional LVDS FIFO status
channel configuration, implementers should refer to the LVDS data path AC timing parameters
Parameter
Min
Max
Units
Transmitter
Channel-to-Channel Skew 1
1. Guaranteed by design.
N/A
100
ps
N/A
50
ps
N/A
100
ps
N/A
50
ps
TCLK Duty Cycle when sourced
45
55
%
TCLK Duty Cycle when sourced
2. When TCLK_REF is selected as the TCLK source, the TCLK_REF duty cycle must be held to within 47.5% to 52.5% to main-
tain the 45% to 55% output duty cycle; otherwise, the TCLK duty cycle will be equal to the source TCLK_REF duty cycle +/-
2.5%.
45
55
%
TXCCLK Duty Cycle when sourced
45
55
%
TXCCLK Duty Cycle when sourced
3. When TCLK_REF or RCLK is selected as the TXCCLK source, the TCLK_REF/RCLK duty cycle must be held to within 47.5%
to 52.5% to maintain the 45% to 55% output duty cycle; otherwise, the TXCCLK duty cycle will be equal to the source
TCLK_REF/RCLK duty cycle +/- 2.5%.
45
55
%
Receiver
Receiver Data Valid Window
1, 4
4. This parameter specifies the receiver setup/hold requirement. This is equal to three sample periods, and the sample period is
the Bit Time/8. The DLL in the receive path generates 16 unique sample clocks per cycle or 8 sample clocks per bit time. The
receive data valid window must be at least 3 sample clocks wide. For example, at 350 MHz this is ((((1/350)/2))/8)*3 or 536 ps.
3*(Bit Time/8)5
5. The bit time is the 1/Cycle time of the interface divided by 2 for a double data rate bus. For example, at 350 MHz, the bit time
is ((1/350/2) or 1.428 ns.
N/A
ps
Receiver Data Valid Window
1, 6
6. Valid for Interface running at 350 MHz.
536
N/A
ps
Receiver Data Valid Window
1, 7
7. Valid for Interface running at 400 MHz.
469
N/A
ps
Receiver Data Valid Window
1, 8
8. Valid for Interface running at 500 MHz.
375
N/A
ps