C161U
The High-Speed Synchronous Serial Interface
Preliminary Data Sheet
318
02.2000
PRELIMINARY
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PT
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signal is ANDed with the respective port line output latch. Enabling the SSC with an idle-
low clock (SSCPO=’0’) will drive the alternate data output and (via the AND) the port pin
SCLK immediately low. To avoid this, use the following sequence:
select the clock idle level (SSCPO=’x’)
load the port output latch with the desired clock idle level (P3.13=’x’)
switch the pin to output (DP3.13=’1’)
enable the SSC (SSCEN=’1’)
if SSCPO=’0’: enable alternate data output (P3.13=’1’)
The same mechanism as for selecting a slave for transmission (separate select lines or
special commands) may also be used to move the role of the master to another device
in the network. In this case the previous master and the future master (previous slave)
will have to toggle their operating mode (SSCMS) and the direction of their port pins (see
description above).
14.2
Half Duplex Operation
In a half duplex configuration only one data line is necessary for both receiving and
transmitting of data. The data exchange line is connected to both pins MTSR and MRST
of each device, the clock line is connected to the SCLK pin.
The master device controls the data transfer by generating the shift clock, while the slave
devices receive it. Due to the fact that all transmit and receive pins are connected to the
one data exchange line, serial data may be moved between arbitrary stations.
Similar to full duplex mode there are two ways to avoid collisions on the data
exchange line:
only the transmitting device may enable its transmit pin driver
the non-transmitting devices use open drain output and only send ones.
Since the data inputs and outputs are connected together, a transmitting device will clock
in its own data at the input pin (MRST for a master device, MTSR for a slave). By these
means any corruptions on the common data exchange line are detected, where the
received data is not equal to the transmitted data.