C161U
Central Processor Unit
Preliminary Data Sheet
85
02.2000
PRELIMINARY
PRE
LI
M
INAR
Y
- E
XCE
RP
T
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value, which represents the desired lowest Top of Stack address plus 12 according to
the selected maximum stack size. This considers the worst case that will occur, when a
stack overflow condition is detected just during entry into an interrupt service routine.
Then, six additional stack word locations are required to push IP, PSW, and CSP for both
the interrupt service routine and the hardware trap service routine.
More details about the stack overflow trap service routine and virtual stack management
are given in chapter “System Programming”.
The Stack Underflow Pointer STKUN
This non-bit addressable register is compared against the SP register after each
operation, which pops data from the system stack (eg. POP and RET instructions) and
after each addition to the SP register. If the content of the SP register is greater than the
the content of the STKUN register, a stack underflow hardware trap will occur.
Since the least significant bit of register STKUN is tied to '0' and bits 15 through 12 are
tied to '1' by hardware, the STKUN register can only contain values from F000H to
FFFEH.
STKUN (FE16
H / 0BH)
SFR
Reset Value: FC00
H
The Stack Underflow Trap (entered when (SP) > (STKUN)) may be used in two different
ways:
Fatal error indication treats the stack underflow as a system error through the
associated trap service routine.
Automatic system stack refilling allows to use the system stack as a 'Stack Cache'
for a bigger external user stack. In this case register STKUN should be initialized to a
value, which represents the desired highest Bottom of Stack address.
More details about the stack underflow trap service routine and virtual stack
management are given in chapter “System Programming”.
Bit
Function
stkun
Modifiable portion of register STKUN
Specifies the upper limit of the internal system stack.
1
0
1
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
r
rw
r
11
r
stkun