C161U
System Control Unit (CSCU)
Preliminary Data Sheet
396
02.2000
PRELIMINARY
PRE
LI
M
INAR
Y
- E
XC
ER
PT
-
Note: SYSCON2 is a security register. The security level is automatically set to write
protectection after execution of EINIT.
Note: To be compatibile to Infineon’s C167CR / 167CS, the Power Down Control
PDCON must be programmed to ’10’ (RTC = Off, Ports = On) during the
initialisation phase before the execution of EINIT instruction. The initial state after
reset is so defined that a reset does not interrupt the real time clock.
20.6
Peripheral Management Module
This module especially serves for power management support, controlling dynamically
the operation and thus the power consumption of the different peripherals on PD Bus
and XBUS. In each situation (eg. several system operating modes, standby, etc.) only
those peripherals may be kept running which are required for the respective functionality.
All others can be switched off. It also allows the operation control of whole groups of
peripherals.
Peripheral’s operation is disabled or enabled by controlling the specific clock input. This
function also is supported in idle and/or slow down mode.
Bit
Function
PDCON
Power Down Control (during power down mode)
x0:
RTC = Off, Ports = On (default after reset).
x1:
RTC = Off, Ports = Off.
Note: In power down mode, the RTC of the C161U is always off. Bit 5 of
SYSCON2 is don’t care.
RCS
RTC Clock Source (not affected by a reset)
0:
RTC is switched to synchronous mode. The input is derived from the
CPU clock.
1:
RTC is switched to asynchronous mode. The input is derived from the
RTC_REF_CLK (oscillator clock).
SCS
SDD Clock Source (not affected by a reset)
Has to be set to ’0’.
CLKCON
Clock State Control
00:
Running on configured basic frequency.
01:
Running on slow down frequency, PLL ON.
10:
Running on slow down frequency, PLL OFF.
11:
Reserved. Do not use this combination.
CLKREL
Reload Counter Value for Slowdown Divider
CLKLOCK
Clock Signal Status Bit
0:
Main oscillator is unstable or PLL is unlocked.
1:
Main oscillator is stable and PLL is locked.