C161U
System Control Unit (CSCU)
Preliminary Data Sheet
383
02.2000
PRELIMINARY
PRE
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INAR
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XCE
RP
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– Provide stable clock (PLL base frequency of about 4 MHz) during power-on reset
phase while clock signal on XTAL1 is not stabilized, to prevent from uncontrolled
internal cross currents.
Reset control in Flash modules:
– Provide control signal for start delay after reset or wakeup until voltage ramp-up in
Flash module is finished
XBUS Peripheral Configuration Block
In the C161U, XBUS peripherals can be separately switched on or off by programming
the XPERCON register. If switched off, the respective peripheral is not visible, meaning,
that its address space and its functional pins are not occupied.
Note: In parallel to the XPER control with XPERCON register, the visibility of XPER
address spaces also is controlled with the BUSACT bits in respective XBCON
registers (in the C166 core)
Note: The XPER configuration is additionally controlled by means of flexible peripheral
management control (see Peripheral Management Module below) for power
reduction.
Register in XPER Configuration Block:
System Control Block
This block has several system management functions.
The System Control Block controls the system register write protection, introduced for
the system control registers SYSCON1-3.
Note: The new register write protection especially supports modularity of design, and is
therefore not compatible with the previously known C16x release function, using
the release bitfield in SYSCON2 for write protection.
Additional control functions of the System Control Block:
– Control of fast external interrupt inputs
– Control of external interrupt source selection
– Control of interrupt subnode for PLL and realtime clock interrupts
– Control of spike suppression for fast external interrupts and NMI in Sleep mode
– Clock output frequency control
The System Control Block provides the following registers:
:
Register
Description
XPERCON
XBUS peripheral control of XPER visibility