![](http://datasheet.mmic.net.cn/120000/SABC161U-LF_datasheet_3574714/SABC161U-LF_64.png)
C161U
Central Processor Unit
Preliminary Data Sheet
64
02.2000
PRELIMINARY
PRE
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INAR
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PT
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Figure 16
Cache Jump Instruction Pipelining
Particular Pipeline Effects
Since up to four different instructions are processed simultaneously, additional hardware
has been spent in the C161U to consider all causal dependencies which may exist on
instructions in different pipeline stages without a loss of performance. This extra
hardware (ie. for 'forwarding' operand read and write values) resolves most of the
possible conflicts (eg. multiple usage of buses) in a time optimized way and thus avoids
that the pipeline becomes noticeable for the user in most cases. However, there are
some very rare cases, where the circumstance that the C161U is a pipelined machine
requires attention by the programmer. In these cases the delays caused by pipeline
conflicts can be used for other instructions in order to optimize performance.
Context Pointer Updating
An instruction, which calculates a physical GPR operand address via the CP register, is
mostly not capable of using a new CP value, which is to be updated by an immediately
preceding instruction. Thus, to make sure that the new CP value is used, at least one
instruction must be inserted between a CP-changing and a subsequent GPR-using
instruction, as shown in the following example:
I
n
: SCXT CP, #0FC00h
; select a new context
I
n+1
: ....
; must not be an instruction using a GPR
I
n+2
: MOV R0, #dataX
; write to GPR 0 in the new context
Data Page Pointer Updating
An instruction, which calculates a physical operand address via a particular DPPn (n=0
to 3) register, is mostly not capable of using a new DPPn register value, which is to be
I
n+2
Cache Jmp
I
n
. . .
I
TARGET+1
I
TARGET
Cache Jmp
I
n
I
TARGET+2
I
TARGET+1
I
TARGET
Cache Jmp
I
n+2
Cache Jmp
I
n
. . .
I
TARGET
(I
INJECT)
Cache Jmp
I
n
I
TARGET+1
I
TARGET
(I
INJECT)
Cache Jmp
1 Machine
Cycle
FETCH
DECODE
EXECUTE
WRITEBACK
1st loop iteration
Injection
Injection of cached
Target Instruction
Repeated loop iteration