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C161U
System Control Unit (CSCU)
Preliminary Data Sheet
388
02.2000
PRELIMINARY
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case of an external reset additionally with the HW-reset signal HWRST. For latching of
system startup configuration the lengthened reset type indication (SWR/WDTR or
SHWR) is additionally provided to the System Configuration Block of CSCU and to the
C166 core.
For acceleration of test operations the reset sequence execution is disabled in function
test mode (TMA) and in scan test mode (TMB). In that case the external HW reset must
have a minimum hold time of 16 TCL (@ 36 MHz).
20.3.3
Reset Lengthening Control (Start Delay)
In case of a hardware reset the internal system reset time as controlled with the external
reset input RSTIN (long HW-reset) or with the reset sequence time (short HW-reset) will
be lengthened if the internal clocking system (oscillator and PLL) is still not stabilized
(see above). In this case the internal system reset signal RST is lengthened and the
execution of first instruction after reset is delayed until the PLL is stabilized.
Note: The start delay because of clock system rampup and stabilisation time also has to
be considered in case of wakeup from Sleep or Idle mode. In these cases the start
is not delayed by reset lengthening; but a setup-active signal is provided to the
core to delay the execution of first instruction (system hold is lengthened by start
delay of clock distribution).
The reset(setup) lengthening conditions are indicated to the CSCU by dedicated
lengthening or busy signals. The total time of the conditions delaying the execution of
first instruction after reset or wakeup is called the setup time.
Note: The above described lengthening conditions for setup control do not lengthen the
sampling time of startup configuration and the bidirectional reset on RSTIN pin
(both are controlled with the HWRST reset signal).
20.4
XBUS Peripheral Configuration Block
The XBUS peripherals can be separately selected for being visible to the user by means
of corresponding selection bits in the XPERCON register. If not selected and therefore
not enabled (not activated with XPERCON bit), the peripheral’s address space including
SFR addresses and port pins are not occupied by the peripheral, thus the peripheral is
not visible and not available. To make an XBUS peripheral visible, its related bit in
XPERCON register must be set before the XPERs are globally enabled with XPEN-bit
in SYSCON register (during system initialization before EINIT instruction).
Note: After reset, no XBUS peripheral is selected in XPERCON register.