C161U
Power Reduction Modes
Preliminary Data Sheet
374
02.2000
PRELIMINARY
PRE
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M
INAR
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XC
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PT
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Figure 119
Transitions between Idle mode and active mode
Idle mode can also be terminated by a Non-Maskable Interrupt, ie. a high to low transition
on the NMI pin. After Idle mode has been terminated by an interrupt or NMI request, the
interrupt system performs a round of prioritization to determine the highest priority
request. In the case of an NMI request, the NMI trap will always be entered.
Any interrupt request whose individual Interrupt Enable flag was set before Idle mode
was entered will terminate Idle mode regardless of the current CPU priority. The CPU
will not go back into Idle mode when a CPU interrupt request is detected, even when the
interrupt was not serviced because of a higher CPU priority or a globally disabled
interrupt system (IEN=’0’). The CPU will only go back into Idle mode when the interrupt
system is globally enabled (IEN=’1’) and a PEC service on a priority level higher than
the current CPU level is requested and executed.
Note: An interrupt request which is individually enabled and assigned to priority level 0
will terminate Idle mode. The associated interrupt vector will not be accessed,
however.
The watchdog timer may be used to monitor the Idle mode: an internal reset will be
generated if no interrupt or NMI request occurs before the watchdog timer overflows. To
prevent the watchdog timer from overflowing during Idle mode it must be programmed
to a reasonable time interval before Idle mode is entered.
19.2
Power Down Mode
To further reduce the power consumption the microcontroller can be switched to Power
Down mode. Clocking of all internal blocks is stopped, the contents of the internal RAM,
however, are preserved through the voltage supplied via the VCC pins. The watchdog
Active
Mode
Idle
Mode
IDLE instruction
CPU Interrupt Request
Denied PEC Request
Executed
PEC Request
denied
accepted