C161U
System Reset
Preliminary Data Sheet
369
02.2000
PRELIMINARY
PRE
LI
M
INAR
Y
- E
XCE
RP
T
-
used to indicate the end of the initialization routine and the proper operation of the
microcontroller to external hardware.
Note: All configurations regarding register SYSCON (enable CLKOUT, stacksize, etc.)
must be selected before the execution of EINIT.
18.1
System Startup Configuration
Although most of the programmable features of the C161U are either selected during the
initialization phase or repeatedly during program execution, there are some features that
must be selected earlier, because they are used for the first access of the program
execution (eg. internal or external start selected via EA).
These selections are made during reset via the pins of PORT0, which are read at the
end of the internal reset sequence. During reset internal pullup devices are active on the
PORT0 lines, so their input level is high, if the respective pin is left open, or is low, if the
respective pin is connected to an external pulldown device. With the coding of the
selections, as shown below, in many cases the default option, ie. high level, can be used.
The value on the upper byte of PORT0 (P0H) is latched into register RP0H upon reset,
the value on the lower byte (P0L) directly influences the BUSCON0 register (bus mode)
or the internal control logic of the C161U.
Figure 118
PORT0 Configuration during Reset
The pins that control the operation of the internal control logic and the reserved pins are
evaluated only during a hardware triggered reset sequence. The pins that influence the
configuration of the C161U are evaluated during any reset sequence, ie. also during
software and watchdog timer triggered resets.
-
ADP
WRC
L.5
L.4
L.3
L.2
L.1
L.0
H.3 H.2 H.1 H.0 L.7
L.6
H.7 H.6 H.5 H.4
CSSEL
SALSEL
BUSTYP
RP
0H
Port 4
Logic
Port 6
Logic
SYSCON
BUSCON0
Internal Control Logic
(Only on hardware reset)
CLKCFG
Clock
Generator
(Only on
hardware reset)
SMOD