C161U
Central Processor Unit
Preliminary Data Sheet
60
02.2000
PRELIMINARY
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The on-chip peripheral units of the C161U work nearly independent of the CPU with a
separate clock generator. Data and control information is interchanged between the
CPU and these peripherals via Special Function Registers (SFRs). Whenever
peripherals need a non-deterministic CPU action, an on-chip Interrupt Controller
compares all pending peripheral service requests against each other and prioritizes one
of them. If the priority of the current CPU operation is lower than the priority of the
selected peripheral request, an interrupt will occur.
Basically, there are two types of interrupt processing:
Standard interrupt processing forces the CPU to save the current program status
and the return address on the stack before branching to the interrupt vector jump table.
PEC interrupt processing steals just one machine cycle from the current CPU activity
to perform a single data transfer via the on-chip Peripheral Event Controller (PEC).
System errors detected during program execution (socalled hardware traps) or an
external non-maskable interrupt are also processed as standard interrupts with a very
high priority.
In contrast to other on-chip peripherals, there is a closer conjunction between the
watchdog timer and the CPU. If enabled, the watchdog timer expects to be serviced by
the CPU within a programmable period of time, otherwise it will reset the chip. Thus, the
watchdog timer is able to prevent the CPU from going totally astray when executing
erroneous code. After reset, the watchdog timer starts counting automatically, but it can
be disabled via software, if desired.
Beside its normal operation there are the following particular CPU states:
Reset state: Any reset (hardware, software, watchdog) forces the CPU into a
predefined active state.
IDLE state: The clock signal to the CPU itself is switched off, while the clocks for the
on-chip peripherals keep running.
POWER DOWN state: All of the on-chip clocks are switched off.
A transition into an active CPU state is forced by an interrupt (if being IDLE) or by a reset
(if being in POWER DOWN mode).
The IDLE, POWER DOWN and RESET states can be entered by particular C161U
system control instructions.
A set of Special Function Registers is dedicated to the functions of the CPU core:
General System Configuration: SYSCON (RP0H)
CPU Status Indication and Control: PSW
Code Access Control: IP, CSP
Data Paging Control: DPP0, DPP1, DPP2, DPP3
GPRs Access Control: CP