C161U
Interrupt and Trap Functions
Preliminary Data Sheet
125
02.2000
PRELIMINARY
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A few examples illustrate these delays:
The worst case interrupt response time including external accesses will occur, when
instructions N, N+1 and N+2 are executed out of external memory, instructions N-1 and
N require external operand read accesses, instructions N-3 through N write back
external operands, and the interrupt vector also points to an external location. In this
case the interrupt response time is the time to perform 9 word bus accesses, because
instruction I1 cannot be fetched via the external bus until all write, fetch and read
requests of preceding instructions in the pipeline are terminated.
When the above example has the interrupt vector pointing into the internal code
memory, the interrupt response time is 7 word bus accesses plus 2 states, because
fetching of instruction I1 from internal code memory can start earlier.
When instructions N, N+1 and N+2 are executed out of external memory and the
interrupt vector also points to an external location, but all operands for instructions N-3
through N are in internal memory, then the interrupt response time is the time to perform
3 word bus accesses.
When the above example has the interrupt vector pointing into the internal code
memory, the interrupt response time is 1 word bus access plus 4 states.
After an interrupt service routine has been terminated by executing the RETI instruction,
and if further interrupts are pending, the next interrupt service routine will not be entered
until at least two instruction cycles have been executed of the program
that was
interrupted. In most cases two instructions will be executed during this time. Only one
instruction will typically be executed, if the first instruction following the RETI instruction
is a branch instruction (without cache hit), or if it reads an operand from internal code
memory, or if it is executed out of the internal RAM.
Note: A bus access in this context includes all delays which can occur during an external
bus cycle.
7.7
PEC Response Times
The PEC response time defines the time from an interrupt request flag of an enabled
interrupt source being set until the PEC data transfer being started. The basic PEC
response time for the C161U is 2 instruction cycles.