C161U
Instruction Set Summary
Preliminary Data Sheet
439
02.2000
PRELIMINARY
PRE
LI
M
INAR
Y
- E
XCE
RP
T
-
Entering the Power Down mode:
PWRDN
Servicing the Watchdog Timer:
SRVWDT
Disabling the Watchdog Timer:
DISWDT
Signifying the end of the initialization routine
(pulls pin RSTOUT high, and disables the effect of
any later execution of a DISWDT instruction):
EINIT
Miscellaneous
Null operation which requires 2 bytes of
storage and the minimum time for execution:
NOP
Definition of an unseparable instruction sequence:
ATOMIC
Switch ‘reg’, ‘bitoff’ and ‘bitaddr’ addressing modes
to the Extended SFR space:
EXTR
Override the DPP addressing scheme
using a specific data page instead of the DPPs,
and optionally switch to ESFR space:
EXTP
EXTPR
Override the DPP addressing scheme
using a specific segment instead of the DPPs,
and optionally switch to ESFR space:
EXTS
EXTSR
Note: The ATOMIC and EXT* instructions provide support for uninterruptable code
sequences eg. for semaphore operations. They also support data addressing
beyond the limits of the current DPPs (except ATOMIC), which is advantageous
for bigger memory models in high level languages. Refer to chapter “System
Programming” for examples.
Protected Instructions
Some instructions of the C161U which are critical for the functionality of the controller
are implemented as so-called Protected Instructions. These protected instructions use
the maximum instruction format of 32 bits for decoding, while the regular instructions
only use a part of it (eg. the lower 8 bits) with the other bits providing additional
information like involved registers. Decoding all 32 bits of a protected doubleword
instruction increases the security in cases of data distortion during instruction fetching.
Critical operations like a software reset are therefore only executed if the complete
instruction is decoded without an error. This enhances the safety and reliability of a
microcontroller system.