C161U
Central Processor Unit
Preliminary Data Sheet
94
02.2000
PRELIMINARY
PRE
LI
M
INAR
Y
- E
XC
ER
PT
-
in packet transfer mode, a COUNT2 value change from 0001H to 0000H in a linked PEC
channel and the CL flag is set in the respective PEC control register.
In these cases the CPU is requested to update the PEC control and pointer registers
while the next block transfer is executed. The last block transfer is determined by the
missing link bit in the linked PEC control register. If a service request hits a linked
channel with a COUNT field equal to 00H and the channel link flag disabled, a standard
interrupt is performed as known from standard PEC channels.
CLISNC (FFA8
H / D4H)
SFR
Reset Value: 0000
H
The Packet Transfer control bit PT is implemented only in PECC0 and PECC1. When
set to ’1’, this bit enables the Packet Transfer mode. In this mode, each service request
initiates the transfer of an entire data packet of a fixed size. The COUNT field in the
PECCx register is used to define the size of the packet (in number of bytes or words
depending on the value of BWT). Therefore packets up to 256 bytes/words may be
transfered.
The register PECXC0/1 is then used to specify the number of requests to be serviced by
a PEC packet transfer before activating the interrupt service routine, which is associated
with the priority level. After each PEC packet transfer, the COUNT2 field is decremented
and the request flag is cleared, and then when COUNT2 reaches 0000H, an interrupt
request is generated to the corresponding interrupt vector.
Note: In the C161U, the packet size is limited to 1. Packet transfers are not supported,
but the extended transfer count COUNT2 is used when PT bit is set.
Bit
Function
xxIE
Channel Link Interrupt Enable Bit (individual for each pair of linked channels)
’0’: Interrupt request disabled
’1’: Interrupt request enabled
xxIR
Channel Service Request Flag
’0’: No channel link service request pending
’1’: The channel pair has raised a request to service a PEC channel after
channel link
-
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
-
rw
-
rw
-
rw
-
C6
IR
C2
IE
C0
IR
-
rw
-
C6
IE
rw
C2
IR
C0
IE
C4
IR
C4
IE