C161U
Memory Organization
Preliminary Data Sheet
53
02.2000
PRELIMINARY
PRE
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RP
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General Purpose Registers
The General Purpose Registers (GPRs) use a block of 16 consecutive words within the
internal RAM. The Context Pointer (CP) register determines the base address of the
currently active register bank. This register bank may consist of up to 16 word GPRs (R0,
R1, ..., R15) and/or of up to 16 byte GPRs (RL0, RH0, ..., RL7, RH7). The sixteen byte
GPRs are mapped onto the first eight word GPRs (see table below).
In contrast to the system stack, a register bank grows from lower towards higher address
locations and occupies a maximum space of 32 Byte. The GPRs are accessed via short
2-, 4- or 8-bit addressing modes using the Context Pointer (CP) register as base address
(independent of the current DPP register contents). Additionally, each bit in the currently
active register bank can be accessed individually.
Mapping of General Purpose Registers to RAM Addresses
The C161U supports fast register bank (context) switching. Multiple register banks can
physically exist within the internal RAM at the same time. Only the register bank selected
by the Context Pointer register (CP) is active at a given time, however. Selecting a new
active register bank is simply done by updating the CP register. A particular Switch
Context (SCXT) instruction performs register bank switching and an automatic saving of
the previous context. The number of implemented register banks (arbitrary sizes) is only
limited by the size of the available internal RAM.
Internal RAM Address
Byte Registers
Word Register
<CP> + 1E
H
---
R15
<CP> + 1C
H
---
R14
<CP> + 1A
H
---
R13
<CP> + 18
H
---
R12
<CP> + 16
H
---
R11
<CP> + 14
H
---
R10
<CP> + 12
H
---
R9
<CP> + 10
H
---
R8
<CP> + 0E
H
RH7
RL7
R7
<CP> + 0C
H
RH6
RL6
R6
<CP> + 0A
H
RH5
RL5
R5
<CP> + 08
H
RH4
RL4
R4
<CP> + 06
H
RH3
RL3
R3
<CP> + 04
H
RH2
RL2
R2
<CP> + 02
H
RH1
RL1
R1
<CP> + 00
H
RH0
RL0
R0