C161U
System Control Unit (CSCU)
Preliminary Data Sheet
382
02.2000
PRELIMINARY
PRE
LI
M
INAR
Y
- E
XC
ER
PT
-
Reset Control Block
The system Reset Control Block generally controls system reset, setup and execution
start operation. It provides the reset signals for correct initialization of the C161U into the
defined reset state. In the C161U, the reset operation is mainly controlled in this Reset
Control Block, but partly also in the C166 core and other system blocks, as follows:
Reset control in Reset Control Block:
– Synchronization and buffering of asynchronous HW reset on RSTIN input
– Generation of synchronized system reset signal RST, out of RSTIN, SW or WDT
reset
– Distribution of asynchronous (only leading edge) HW reset signal to the pads and
for start (enable) of oscillator and PLL
– Control of minimum reset duration of 25sec (can be disabled in function testmode)
for latching of startup/reset configuration from P0 with execution of the so called
reset sequence of 2048/4096 TCL (1024/2048 CPU clock cycles); after completion
of reset sequence the internal reset condition may be prolonged until RSTIN pin
gets inactive (in case of HW reset).
– Control of reset lengthening for start delay after reset because of not stabilized PLL
clock or/and Flash voltages
– Provide power-on reset signal for WDT and RTC. Note: The power-on detection is
performed outside the CSCU.
– Provide reset type indication (HW or SW/WDT reset) for latching of system startup
configuration
– Provide spike suppression on RSTIN pin with input filter; input signals shorter than
10ns are suppressed, detection is guaranteed for minimum 150ns reset signals.
– Disable reset sequence execution in CPU functional test mode
Reset control in CB-Core:
– Generation of SW reset signal
– Immediate cancelling of pending internal hold states
– Immediate abortion of bus cycle exept for WDT reset
– Generation of WDT reset active signal
– Control of reset output on RSTOUT pin, activated until the execution of EINIT
instruction
Reset control in Watchdog Timer module:
– Generation of WDT reset
– Indication of reset sources in WDT control register
Reset control in Clock Generation Unit and PLL:
– Provide control signal for reset lengthening until oscillator and PLL have been
stabilized in the dedicated frequency (start delay)