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C161U
System Control Unit (CSCU)
Preliminary Data Sheet
386
02.2000
PRELIMINARY
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The duration of 2048 TCL is determined by the internal reset sequence (see below) and
by the necessary sampling time (25 sec) for the startup configuration on port P0. In
case of enabled bidirectional RSTIN function (controlled with bit 3 of the SYSCON
register), the reset types SWR, WDTR and the internally lengthened SHWR are reported
to external system.
External Hardware Reset
The CSCU provides spike suppression for RSTIN pin with an input filter; input signals
shorter than 10ns are suppressed, detection is guaranteed for minimum 150ns reset
signals. The filtered and stable HW reset signal is buffered and distributed by the CSCU
to the core and to the other modules including the pads (signal RST). This internal
system reset signal uses directly the filtered, but asynchronous RSTIN signal for its
activation. Its trailing edge (deactivation) is determined either
– by the synchronized trailing edge of the RSTIN input (hardware reset), or
– by termination of the reset sequence (see below), if still running when RSTIN is
deactivated, or
– by termination of the internal lengthening condition, e.g. osc/PLL stabilisation time
(see below).
With deactivation of the internal RST signal, program execution is started in the core.
Additionally to the system reset signal RST, the Reset Control Block provides the
hardware reset signal HWRST which also has only the trailing edge synchronized, but
which is not lengthened in case of an active lengthening condition. This asynchronous
but filtered HW-reset signal is used to enable the oscillator and PLL, and to start (with
trailing edge of HWRST) ramp-up of Flash memories. HWRST is also used for
immediate switch of pad drivers into the tristate condition independently of the availability
of the internal clock.
During oscillator stabilization phase after power-on the system is supplied with the PLL
base clock (about 5 MHz) which is generated with power-on (about 100sec delay) and
enabled with HWRST.
Two different kinds of external hardware resets are considered:
– Long Hardware Reset
A long hardware reset requires an active RSTIN time longer than the duration of the
internal reset sequence. The duration of the internal reset sequence is 2048 TCL.
After the internal reset sequence has been completed, the RSTIN input is sampled.
As long as the reset input is still active the internal reset condition is prolonged.
Accordingly, the internal HWRST is active until the external reset on RSTIN input
gets inactive. The long hardware reset type is indicated to the WDT block.
Note: The hardware reset is also used for wakeup from power down state; in this
case the internal system reset will be lengthened (execution of 1. instruction
delayed) until the oscillator and PLL have been stabilized.