C161U
DMA - External PEC (EPEC)
Preliminary Data Sheet
97
02.2000
PRELIMINARY
PRE
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M
INAR
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XCE
RP
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6
DMA - External PEC (EPEC)
The EPEC provides fast and easy means to transfer single data between any memory
location within the address space by using the XBUS. The advantages are reduced
XBUS protocol handling and capability of addressing all system resources including
internal RAM and SFR.
6.1
EPEC Functionality
The EPEC provides a DMA controller for the USB device core to provide fast and flexible
data tranfer capability. The EPEC is implemented as a 16 channel controller with a 24-
bit source pointer, a 24-bit destination pointer and a 10-bit Transmit Byte Length Counter
with auto-increment support of two bytes (one word) per channel with Terminal Count
(TC) indication (Interrupt pulse valid for one clock cycle). After TC is reached, the counter
stops itself.
The EPEC is connected to the XBUS and to a proprietary 24-bit bus connected directly
to the C166 CBC. The EPEC has the highest priority among other interrupts and PECs
and does not participate in the interrupt priorization round. In case of an DPEC/EPEC
collision, the DPEC will get priority and one instruction cycle later the EPEC is
processed. The EPEC provides DMA like functionality by injecting a memory transfer
instruction (mov [dest], [src]) into the decode stage of the pipeline and thus only needs
one additional instruction cycle. Even in IDLE mode, the EPEC will be processed waking
up the CPU for one instruction cycle and immediately going back to IDLE state.
6.2
EPEC Implementation
The EPEC control block is located in the CBC core with its main purpose to synchronize
the external EPEC request to the internal T1-T4 states of the CPU and the priorization
between DPEC and EPEC. It also drives the externally provided 24-bit source and
destination pointer values on the internal memory address bus, thus controlling the
whole timing with respect to the CPU.
The EPEC Block diagram is shown in Figure 21 below.