C161U
The Watchdog Timer (WDT)
Preliminary Data Sheet
355
02.2000
PRELIMINARY
PRE
LI
M
INAR
Y
- E
XCE
RP
T
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16.1
Operation of the Watchdog Timer
The current count value of the Watchdog Timer is contained in the Watchdog Timer
Register WDT, which is a non-bitaddressable read-only register. The operation of the
Watchdog Timer is controlled by its bitaddressable Watchdog Timer Control Register
WDTCON. This register specifies the reload value for the high byte of the timer, selects
the input clock prescaling factor and provides a flag that indicates a watchdog timer
overflow.
WDTCON (FFAE
H / D7H)
SFR
Reset Value: 000X
H
Note: The reset value will be 0002H, if the reset was triggered by the watchdog timer
(overflow). It will be 0000H otherwise.
After any software reset, external hardware reset (see note), or watchdog timer reset,
the watchdog timer is enabled and starts counting up from 0000H with the frequency fCPU/
2. The input frequency may be switched to fCPU/128 by setting bit WDTIN. The watchdog
timer can be disabled via the instruction DISWDT (Disable Watchdog Timer). Instruction
DISWDT is a protected 32-bit instruction which will ONLY be executed during the time
between a reset and execution of either the EINIT (End of Initialization) or the SRVWDT
(Service Watchdog Timer) instruction. Either one of these instructions disables the
execution of DISWDT.
Bit
Function
WDTIN
Watchdog Timer Input Frequency Selection
‘0’: Input frequency is f
CPU / 2
‘1’: Input frequency is f
CPU / 128
WDTR
Watchdog Timer Reset Indication Flag
Set by the watchdog timer on an overflow.
Cleared by the SRVWDT instruction.
SWR
Software Reset
Set by the command SRST
SHWR
Short Hardware Reset
Set by the input RSTIN
LHWR
Long Hardware Reset
Set by the input RSTIN
reserved
Reserved
These bits are reserved
WDTREL
Watchdog Timer Reload Value (for the high byte)
SHW
R
WDT
R
SWR
WDT
IN
LHW
R
5
4
3
2
1
0
11
10
9
8
7
6
15
14
13
12
r
rw
-
WDTREL
rw
r
-
RESERVED